7034228792
Having received another series of whitespace patches I decided to do this once and for all rather than dealing with this kind of patches trickling in forever. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
69 lines
2.1 KiB
C
69 lines
2.1 KiB
C
/*
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* Copyright (C) 2000, 2001 Broadcom Corporation
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#include <linux/clocksource.h>
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#include <asm/addrspace.h>
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#include <asm/io.h>
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#include <asm/time.h>
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#include <asm/sibyte/sb1250.h>
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#include <asm/sibyte/sb1250_regs.h>
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#include <asm/sibyte/sb1250_int.h>
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#include <asm/sibyte/sb1250_scd.h>
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#define SB1250_HPT_NUM 3
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#define SB1250_HPT_VALUE M_SCD_TIMER_CNT /* max value */
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/*
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* The HPT is free running from SB1250_HPT_VALUE down to 0 then starts over
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* again.
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*/
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static cycle_t sb1250_hpt_read(struct clocksource *cs)
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{
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unsigned int count;
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count = G_SCD_TIMER_CNT(__raw_readq(IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, R_SCD_TIMER_CNT))));
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return SB1250_HPT_VALUE - count;
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}
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struct clocksource bcm1250_clocksource = {
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.name = "bcm1250-counter-3",
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.rating = 200,
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.read = sb1250_hpt_read,
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.mask = CLOCKSOURCE_MASK(23),
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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void __init sb1250_clocksource_init(void)
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{
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struct clocksource *cs = &bcm1250_clocksource;
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/* Setup hpt using timer #3 but do not enable irq for it */
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__raw_writeq(0,
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IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM,
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R_SCD_TIMER_CFG)));
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__raw_writeq(SB1250_HPT_VALUE,
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IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM,
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R_SCD_TIMER_INIT)));
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__raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
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IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM,
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R_SCD_TIMER_CFG)));
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clocksource_register_hz(cs, V_SCD_TIMER_FREQ);
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}
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