c5aa59e88f
Add support for cn68xx, cn61xx, cn63xx, cn66xx and cnf71XX. Add little-endian register layouts. Patch cvmx-interrupt-rsl.c for changed definition. Signed-off-by: David Daney <david.daney@cavium.com>
105 lines
2.7 KiB
C
105 lines
2.7 KiB
C
/***********************license start***************
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* Author: Cavium Networks
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*
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* Contact: support@caviumnetworks.com
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* This file is part of the OCTEON SDK
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*
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* Copyright (c) 2003-2012 Cavium Networks
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*
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* This file is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, Version 2, as
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* published by the Free Software Foundation.
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*
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* This file is distributed in the hope that it will be useful, but
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* AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
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* NONINFRINGEMENT. See the GNU General Public License for more
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* details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this file; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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* or visit http://www.gnu.org/licenses/.
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*
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* This file may also be available under a different license from Cavium.
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* Contact Cavium Networks for more information
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***********************license end**************************************/
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#ifndef __CVMX_DBG_DEFS_H__
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#define __CVMX_DBG_DEFS_H__
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#define CVMX_DBG_DATA (CVMX_ADD_IO_SEG(0x00011F00000001E8ull))
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union cvmx_dbg_data {
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uint64_t u64;
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struct cvmx_dbg_data_s {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_23_63:41;
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uint64_t c_mul:5;
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uint64_t dsel_ext:1;
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uint64_t data:17;
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#else
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uint64_t data:17;
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uint64_t dsel_ext:1;
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uint64_t c_mul:5;
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uint64_t reserved_23_63:41;
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#endif
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} s;
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struct cvmx_dbg_data_cn30xx {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_31_63:33;
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uint64_t pll_mul:3;
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uint64_t reserved_23_27:5;
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uint64_t c_mul:5;
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uint64_t dsel_ext:1;
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uint64_t data:17;
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#else
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uint64_t data:17;
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uint64_t dsel_ext:1;
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uint64_t c_mul:5;
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uint64_t reserved_23_27:5;
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uint64_t pll_mul:3;
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uint64_t reserved_31_63:33;
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#endif
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} cn30xx;
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struct cvmx_dbg_data_cn30xx cn31xx;
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struct cvmx_dbg_data_cn38xx {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_29_63:35;
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uint64_t d_mul:4;
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uint64_t dclk_mul2:1;
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uint64_t cclk_div2:1;
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uint64_t c_mul:5;
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uint64_t dsel_ext:1;
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uint64_t data:17;
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#else
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uint64_t data:17;
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uint64_t dsel_ext:1;
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uint64_t c_mul:5;
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uint64_t cclk_div2:1;
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uint64_t dclk_mul2:1;
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uint64_t d_mul:4;
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uint64_t reserved_29_63:35;
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#endif
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} cn38xx;
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struct cvmx_dbg_data_cn38xx cn38xxp2;
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struct cvmx_dbg_data_cn30xx cn50xx;
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struct cvmx_dbg_data_cn58xx {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_29_63:35;
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uint64_t rem:6;
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uint64_t c_mul:5;
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uint64_t dsel_ext:1;
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uint64_t data:17;
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#else
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uint64_t data:17;
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uint64_t dsel_ext:1;
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uint64_t c_mul:5;
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uint64_t rem:6;
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uint64_t reserved_29_63:35;
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#endif
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} cn58xx;
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struct cvmx_dbg_data_cn58xx cn58xxp1;
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};
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#endif
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