f9b4df4a4d
We add a variant to initalize the interrupt controller in case we describe the GIC using the Device Tree and not platform data. Signed-off-by: Bastian Hecht <hechtb+renesas@gmail.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
68 lines
2.2 KiB
C
68 lines
2.2 KiB
C
/*
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* R8A7740 processor support
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*
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* Copyright (C) 2011 Renesas Solutions Corp.
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* Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/irqchip.h>
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#include <linux/irqchip/arm-gic.h>
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static void __init r8a7740_init_irq_common(void)
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{
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void __iomem *intc_prio_base = ioremap_nocache(0xe6900010, 0x10);
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void __iomem *intc_msk_base = ioremap_nocache(0xe6900040, 0x10);
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void __iomem *pfc_inta_ctrl = ioremap_nocache(0xe605807c, 0x4);
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/* route signals to GIC */
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iowrite32(0x0, pfc_inta_ctrl);
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/*
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* To mask the shared interrupt to SPI 149 we must ensure to set
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* PRIO *and* MASK. Else we run into IRQ floods when registering
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* the intc_irqpin devices
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*/
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iowrite32(0x0, intc_prio_base + 0x0);
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iowrite32(0x0, intc_prio_base + 0x4);
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iowrite32(0x0, intc_prio_base + 0x8);
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iowrite32(0x0, intc_prio_base + 0xc);
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iowrite8(0xff, intc_msk_base + 0x0);
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iowrite8(0xff, intc_msk_base + 0x4);
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iowrite8(0xff, intc_msk_base + 0x8);
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iowrite8(0xff, intc_msk_base + 0xc);
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iounmap(intc_prio_base);
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iounmap(intc_msk_base);
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iounmap(pfc_inta_ctrl);
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}
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void __init r8a7740_init_irq_of(void)
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{
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irqchip_init();
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r8a7740_init_irq_common();
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}
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void __init r8a7740_init_irq(void)
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{
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void __iomem *gic_dist_base = ioremap_nocache(0xc2800000, 0x1000);
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void __iomem *gic_cpu_base = ioremap_nocache(0xc2000000, 0x1000);
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/* initialize the Generic Interrupt Controller PL390 r0p0 */
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gic_init(0, 29, gic_dist_base, gic_cpu_base);
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r8a7740_init_irq_common();
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}
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