a92a5d0dce
This adds support for an ARC Virtual Platform. This platform is based on the System C standard promoted by the OSCI (Open System C Initiative) and uses nSIM to simulate the ARC CPU core itself. Users can build a virtual SoC by combining System C models of peripherals and CPU cores. Signed-off-by: Mischa Jonker <mjonker@synopsys.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
77 lines
1.5 KiB
Text
77 lines
1.5 KiB
Text
/*
|
|
* Copyright (C) 2013 Synopsys, Inc. (www.synopsys.com)
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License version 2 as
|
|
* published by the Free Software Foundation.
|
|
*/
|
|
/dts-v1/;
|
|
|
|
/include/ "skeleton.dtsi"
|
|
|
|
/ {
|
|
compatible = "snps,nsimosci";
|
|
clock-frequency = <80000000>; /* 80 MHZ */
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
interrupt-parent = <&intc>;
|
|
|
|
chosen {
|
|
bootargs = "console=tty0 consoleblank=0";
|
|
};
|
|
|
|
aliases {
|
|
serial0 = &uart0;
|
|
};
|
|
|
|
memory {
|
|
device_type = "memory";
|
|
reg = <0x80000000 0x10000000>; /* 256M */
|
|
};
|
|
|
|
fpga {
|
|
compatible = "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
/* child and parent address space 1:1 mapped */
|
|
ranges;
|
|
|
|
intc: interrupt-controller {
|
|
compatible = "snps,arc700-intc";
|
|
interrupt-controller;
|
|
#interrupt-cells = <1>;
|
|
};
|
|
|
|
uart0: serial@c0000000 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0xc0000000 0x2000>;
|
|
interrupts = <11>;
|
|
#clock-frequency = <80000000>;
|
|
clock-frequency = <3686400>;
|
|
baud = <115200>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
status = "okay";
|
|
};
|
|
|
|
pgu0: pgu@c9000000 {
|
|
compatible = "snps,arcpgufb";
|
|
reg = <0xc9000000 0x400>;
|
|
};
|
|
|
|
ps2: ps2@c9001000 {
|
|
compatible = "snps,arc_ps2";
|
|
reg = <0xc9000400 0x14>;
|
|
interrupts = <13>;
|
|
interrupt-names = "arc_ps2_irq";
|
|
};
|
|
|
|
eth0: ethernet@c0003000 {
|
|
compatible = "snps,oscilan";
|
|
reg = <0xc0003000 0x44>;
|
|
interrupts = <7>, <8>;
|
|
interrupt-names = "rx", "tx";
|
|
};
|
|
};
|
|
};
|