f7f4dc10e1
Signed-off-by: David Howells <dhowells@redhat.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Michael Kerrisk <mtk.manpages@gmail.com> Acked-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com> Acked-by: Dave Jones <davej@redhat.com>
117 lines
2.8 KiB
C
117 lines
2.8 KiB
C
/*
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* linux/include/asm-m32r/ptrace.h
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* M32R version:
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* Copyright (C) 2001-2002, 2004 Hirokazu Takata <takata at linux-m32r.org>
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*/
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#ifndef _UAPI_ASM_M32R_PTRACE_H
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#define _UAPI_ASM_M32R_PTRACE_H
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/* 0 - 13 are integer registers (general purpose registers). */
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#define PT_R4 0
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#define PT_R5 1
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#define PT_R6 2
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#define PT_REGS 3
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#define PT_R0 4
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#define PT_R1 5
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#define PT_R2 6
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#define PT_R3 7
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#define PT_R7 8
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#define PT_R8 9
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#define PT_R9 10
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#define PT_R10 11
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#define PT_R11 12
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#define PT_R12 13
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#define PT_SYSCNR 14
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#define PT_R13 PT_FP
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#define PT_R14 PT_LR
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#define PT_R15 PT_SP
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/* processor status and miscellaneous context registers. */
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#define PT_ACC0H 15
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#define PT_ACC0L 16
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#define PT_ACC1H 17 /* ISA_DSP_LEVEL2 only */
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#define PT_ACC1L 18 /* ISA_DSP_LEVEL2 only */
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#define PT_PSW 19
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#define PT_BPC 20
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#define PT_BBPSW 21
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#define PT_BBPC 22
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#define PT_SPU 23
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#define PT_FP 24
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#define PT_LR 25
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#define PT_SPI 26
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#define PT_ORIGR0 27
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/* virtual pt_reg entry for gdb */
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#define PT_PC 30
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#define PT_CBR 31
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#define PT_EVB 32
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/* Control registers. */
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#define SPR_CR0 PT_PSW
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#define SPR_CR1 PT_CBR /* read only */
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#define SPR_CR2 PT_SPI
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#define SPR_CR3 PT_SPU
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#define SPR_CR4
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#define SPR_CR5 PT_EVB /* part of M32R/E, M32R/I core only */
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#define SPR_CR6 PT_BPC
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#define SPR_CR7
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#define SPR_CR8 PT_BBPSW
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#define SPR_CR9
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#define SPR_CR10
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#define SPR_CR11
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#define SPR_CR12
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#define SPR_CR13 PT_WR
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#define SPR_CR14 PT_BBPC
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#define SPR_CR15
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/* this struct defines the way the registers are stored on the
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stack during a system call. */
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struct pt_regs {
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/* Saved main processor registers. */
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unsigned long r4;
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unsigned long r5;
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unsigned long r6;
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struct pt_regs *pt_regs;
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unsigned long r0;
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unsigned long r1;
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unsigned long r2;
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unsigned long r3;
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unsigned long r7;
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unsigned long r8;
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unsigned long r9;
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unsigned long r10;
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unsigned long r11;
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unsigned long r12;
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long syscall_nr;
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/* Saved main processor status and miscellaneous context registers. */
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unsigned long acc0h;
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unsigned long acc0l;
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unsigned long acc1h; /* ISA_DSP_LEVEL2 only */
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unsigned long acc1l; /* ISA_DSP_LEVEL2 only */
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unsigned long psw;
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unsigned long bpc; /* saved PC for TRAP syscalls */
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unsigned long bbpsw;
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unsigned long bbpc;
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unsigned long spu; /* saved user stack */
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unsigned long fp;
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unsigned long lr; /* saved PC for JL syscalls */
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unsigned long spi; /* saved kernel stack */
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unsigned long orig_r0;
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};
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/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */
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#define PTRACE_GETREGS 12
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#define PTRACE_SETREGS 13
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#define PTRACE_OLDSETOPTIONS 21
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#endif /* _UAPI_ASM_M32R_PTRACE_H */
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