fc18047c73
The ASID is represented as an unsigned int in mm_context_t and we currently use the mmid assembler macro to access this element of the struct. This should be accessed with a register of 32-bit width. If the incorrect register width is used the ASID will be returned in bits[32:63] of the register when running under big-endian. Fix a use of the mmid macro in tlb.S to use a 32-bit access. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Matthew Leach <matthew.leach@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
71 lines
2 KiB
ArmAsm
71 lines
2 KiB
ArmAsm
/*
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* Based on arch/arm/mm/tlb.S
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*
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* Copyright (C) 1997-2002 Russell King
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* Copyright (C) 2012 ARM Ltd.
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* Written by Catalin Marinas <catalin.marinas@arm.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include <asm/asm-offsets.h>
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#include <asm/page.h>
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#include <asm/tlbflush.h>
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#include "proc-macros.S"
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/*
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* __cpu_flush_user_tlb_range(start, end, vma)
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*
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* Invalidate a range of TLB entries in the specified address space.
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*
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* - start - start address (may not be aligned)
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* - end - end address (exclusive, may not be aligned)
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* - vma - vma_struct describing address range
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*/
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ENTRY(__cpu_flush_user_tlb_range)
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vma_vm_mm x3, x2 // get vma->vm_mm
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mmid w3, x3 // get vm_mm->context.id
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dsb sy
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lsr x0, x0, #12 // align address
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lsr x1, x1, #12
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bfi x0, x3, #48, #16 // start VA and ASID
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bfi x1, x3, #48, #16 // end VA and ASID
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1: tlbi vae1is, x0 // TLB invalidate by address and ASID
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add x0, x0, #1
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cmp x0, x1
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b.lo 1b
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dsb sy
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ret
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ENDPROC(__cpu_flush_user_tlb_range)
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/*
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* __cpu_flush_kern_tlb_range(start,end)
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*
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* Invalidate a range of kernel TLB entries.
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*
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* - start - start address (may not be aligned)
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* - end - end address (exclusive, may not be aligned)
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*/
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ENTRY(__cpu_flush_kern_tlb_range)
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dsb sy
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lsr x0, x0, #12 // align address
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lsr x1, x1, #12
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1: tlbi vaae1is, x0 // TLB invalidate by address
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add x0, x0, #1
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cmp x0, x1
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b.lo 1b
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dsb sy
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isb
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ret
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ENDPROC(__cpu_flush_kern_tlb_range)
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