2c1a101965
On i350 VF devices, VLAN tags will be byte-swapped in the receive descriptor only when received packets are looped back from other VFs. Check for this condition and swab the tag if needed. Signed-off-by: Mitch Williams <mitch.a.williams@intel.com> Tested-by: Sibai Li <sibai.li@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
122 lines
4.9 KiB
C
122 lines
4.9 KiB
C
/*******************************************************************************
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Intel(R) 82576 Virtual Function Linux driver
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Copyright(c) 1999 - 2012 Intel Corporation.
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This program is free software; you can redistribute it and/or modify it
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under the terms and conditions of the GNU General Public License,
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version 2, as published by the Free Software Foundation.
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This program is distributed in the hope it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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You should have received a copy of the GNU General Public License along with
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this program; if not, write to the Free Software Foundation, Inc.,
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51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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The full GNU General Public License is included in this distribution in
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the file called "COPYING".
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Contact Information:
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e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
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Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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*******************************************************************************/
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#ifndef _E1000_DEFINES_H_
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#define _E1000_DEFINES_H_
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/* Number of Transmit and Receive Descriptors must be a multiple of 8 */
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#define REQ_TX_DESCRIPTOR_MULTIPLE 8
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#define REQ_RX_DESCRIPTOR_MULTIPLE 8
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/* IVAR valid bit */
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#define E1000_IVAR_VALID 0x80
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/* Receive Descriptor bit definitions */
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#define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */
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#define E1000_RXD_STAT_EOP 0x02 /* End of Packet */
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#define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */
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#define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */
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#define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */
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#define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */
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#define E1000_RXD_STAT_IPCS 0x40 /* IP xsum calculated */
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#define E1000_RXD_ERR_SE 0x02 /* Symbol Error */
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#define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */
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#define E1000_RXDEXT_STATERR_LB 0x00040000
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#define E1000_RXDEXT_STATERR_CE 0x01000000
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#define E1000_RXDEXT_STATERR_SE 0x02000000
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#define E1000_RXDEXT_STATERR_SEQ 0x04000000
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#define E1000_RXDEXT_STATERR_CXE 0x10000000
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#define E1000_RXDEXT_STATERR_TCPE 0x20000000
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#define E1000_RXDEXT_STATERR_IPE 0x40000000
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#define E1000_RXDEXT_STATERR_RXE 0x80000000
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/* Same mask, but for extended and packet split descriptors */
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#define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \
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E1000_RXDEXT_STATERR_CE | \
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E1000_RXDEXT_STATERR_SE | \
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E1000_RXDEXT_STATERR_SEQ | \
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E1000_RXDEXT_STATERR_CXE | \
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E1000_RXDEXT_STATERR_RXE)
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/* Device Control */
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#define E1000_CTRL_RST 0x04000000 /* Global reset */
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/* Device Status */
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#define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */
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#define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */
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#define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */
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#define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */
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#define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */
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#define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */
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#define SPEED_10 10
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#define SPEED_100 100
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#define SPEED_1000 1000
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#define HALF_DUPLEX 1
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#define FULL_DUPLEX 2
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/* Transmit Descriptor bit definitions */
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#define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */
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#define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */
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#define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */
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#define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */
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#define MAX_JUMBO_FRAME_SIZE 0x3F00
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/* 802.1q VLAN Packet Size */
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#define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMA'd) */
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/* Error Codes */
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#define E1000_SUCCESS 0
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#define E1000_ERR_CONFIG 3
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#define E1000_ERR_MAC_INIT 5
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#define E1000_ERR_MBX 15
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/* SRRCTL bit definitions */
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#define E1000_SRRCTL_BSIZEPKT_SHIFT 10 /* Shift _right_ */
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#define E1000_SRRCTL_BSIZEHDRSIZE_MASK 0x00000F00
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#define E1000_SRRCTL_BSIZEHDRSIZE_SHIFT 2 /* Shift _left_ */
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#define E1000_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000
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#define E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000
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#define E1000_SRRCTL_DESCTYPE_MASK 0x0E000000
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#define E1000_SRRCTL_DROP_EN 0x80000000
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#define E1000_SRRCTL_BSIZEPKT_MASK 0x0000007F
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#define E1000_SRRCTL_BSIZEHDR_MASK 0x00003F00
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/* Additional Descriptor Control definitions */
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#define E1000_TXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Tx Queue */
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#define E1000_RXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Rx Queue */
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/* Direct Cache Access (DCA) definitions */
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#define E1000_DCA_TXCTRL_TX_WB_RO_EN (1 << 11) /* Tx Desc writeback RO bit */
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#define E1000_VF_INIT_TIMEOUT 200 /* Number of retries to clear RSTI */
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#endif /* _E1000_DEFINES_H_ */
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