e2c37d9083
The PPC476GTR SoC supports message signalled interrupts (MSI) by writing to special addresses within the High Speed Transfer Assist (HSTA) module. This patch adds support for PCI MSI with a new system device. The DMA window is also updated to allow access to the entire 42-bit address range to allow PCI devices write access to the HSTA module. Signed-off-by: Alistair Popple <alistair@popple.id.au> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
163 lines
4 KiB
C
163 lines
4 KiB
C
/*
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* Copyright © 2013 Tony Breeds IBM Corporation
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* Copyright © 2013 Alistair Popple IBM Corporation
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*
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* Based on earlier code:
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* Copyright (C) Paul Mackerras 1997.
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*
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* Matt Porter <mporter@kernel.crashing.org>
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* Copyright 2002-2005 MontaVista Software Inc.
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*
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* Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
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* Copyright (c) 2003, 2004 Zultys Technologies
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*
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* Copyright 2007 David Gibson, IBM Corporation.
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* Copyright 2010 Ben. Herrenschmidt, IBM Corporation.
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* Copyright © 2011 David Kleikamp IBM Corporation
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <stdarg.h>
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#include <stddef.h>
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#include "types.h"
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#include "elf.h"
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#include "string.h"
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#include "stdlib.h"
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#include "stdio.h"
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#include "page.h"
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#include "ops.h"
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#include "reg.h"
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#include "io.h"
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#include "dcr.h"
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#include "4xx.h"
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#include "44x.h"
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#include "libfdt.h"
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BSS_STACK(4096);
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#define SPRN_PIR 0x11E /* Processor Indentification Register */
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#define USERDATA_LEN 256 /* Length of userdata passed in by PIBS */
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#define MAX_RANKS 0x4
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#define DDR3_MR0CF 0x80010011U
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#define CCTL0_MCO2 0x8000080FU
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#define CCTL0_MCO3 0x80000810U
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#define CCTL0_MCO4 0x80000811U
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#define CCTL0_MCO5 0x80000812U
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#define CCTL0_MCO6 0x80000813U
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static unsigned long long ibm_akebono_memsize;
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static long long unsigned mac_addr;
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static unsigned long long ibm_akebono_detect_memsize(void)
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{
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u32 reg;
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unsigned i;
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unsigned long long memsize = 0;
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for (i = 0; i < MAX_RANKS; i++) {
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reg = mfdcrx(DDR3_MR0CF + i);
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if (!(reg & 1))
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continue;
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reg &= 0x0000f000;
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reg >>= 12;
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memsize += (0x800000ULL << reg);
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}
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return memsize;
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}
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static void ibm_akebono_fixups(void)
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{
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void *emac;
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u32 reg;
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dt_fixup_memory(0x0ULL, ibm_akebono_memsize);
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/* Fixup the SD timeout frequency */
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mtdcrx(CCTL0_MCO4, 0x1);
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/* Disable SD high-speed mode (which seems to be broken) */
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reg = mfdcrx(CCTL0_MCO2) & ~0x2;
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mtdcrx(CCTL0_MCO2, reg);
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/* Set the MAC address */
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emac = finddevice("/plb/opb/ethernet");
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if (emac > 0) {
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if (mac_addr)
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setprop(emac, "local-mac-address",
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((u8 *) &mac_addr) + 2 , 6);
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}
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}
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void platform_init(char *userdata)
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{
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unsigned long end_of_ram, avail_ram;
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u32 pir_reg;
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int node, size;
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const u32 *timebase;
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int len, i, userdata_len;
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char *end;
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userdata[USERDATA_LEN - 1] = '\0';
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userdata_len = strlen(userdata);
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for (i = 0; i < userdata_len - 15; i++) {
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if (strncmp(&userdata[i], "local-mac-addr=", 15) == 0) {
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if (i > 0 && userdata[i - 1] != ' ') {
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/* We've only found a substring ending
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* with local-mac-addr so this isn't
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* our mac address. */
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continue;
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}
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mac_addr = strtoull(&userdata[i + 15], &end, 16);
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/* Remove the "local-mac-addr=<...>" from the kernel
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* command line, including the tailing space if
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* present. */
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if (*end == ' ')
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end++;
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len = ((int) end) - ((int) &userdata[i]);
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memmove(&userdata[i], end,
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userdata_len - (len + i) + 1);
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break;
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}
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}
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loader_info.cmdline = userdata;
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loader_info.cmdline_len = 256;
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ibm_akebono_memsize = ibm_akebono_detect_memsize();
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if (ibm_akebono_memsize >> 32)
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end_of_ram = ~0UL;
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else
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end_of_ram = ibm_akebono_memsize;
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avail_ram = end_of_ram - (unsigned long)_end;
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simple_alloc_init(_end, avail_ram, 128, 64);
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platform_ops.fixups = ibm_akebono_fixups;
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platform_ops.exit = ibm44x_dbcr_reset;
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pir_reg = mfspr(SPRN_PIR);
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/* Make sure FDT blob is sane */
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if (fdt_check_header(_dtb_start) != 0)
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fatal("Invalid device tree blob\n");
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node = fdt_node_offset_by_prop_value(_dtb_start, -1, "device_type",
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"cpu", sizeof("cpu"));
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if (!node)
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fatal("Cannot find cpu node\n");
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timebase = fdt_getprop(_dtb_start, node, "timebase-frequency", &size);
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if (timebase && (size == 4))
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timebase_period_ns = 1000000000 / *timebase;
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fdt_set_boot_cpuid_phys(_dtb_start, pir_reg);
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fdt_init(_dtb_start);
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serial_console_init();
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}
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