dfd871442e
All the clocks controlled by the register 'CCM Serial Clock Multiplexer Register 1' should be fixup clocks. This patch changes those clocks from basic multiplexer or divider clocks to fixup clocks. Signed-off-by: Liu Ying <Ying.Liu@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
65 lines
1.5 KiB
C
65 lines
1.5 KiB
C
#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/of.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include "clk.h"
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DEFINE_SPINLOCK(imx_ccm_lock);
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static struct clk * __init imx_obtain_fixed_clock_from_dt(const char *name)
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{
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struct of_phandle_args phandle;
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struct clk *clk = ERR_PTR(-ENODEV);
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char *path;
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path = kasprintf(GFP_KERNEL, "/clocks/%s", name);
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if (!path)
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return ERR_PTR(-ENOMEM);
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phandle.np = of_find_node_by_path(path);
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kfree(path);
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if (phandle.np) {
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clk = of_clk_get_from_provider(&phandle);
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of_node_put(phandle.np);
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}
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return clk;
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}
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struct clk * __init imx_obtain_fixed_clock(
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const char *name, unsigned long rate)
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{
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struct clk *clk;
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clk = imx_obtain_fixed_clock_from_dt(name);
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if (IS_ERR(clk))
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clk = imx_clk_fixed(name, rate);
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return clk;
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}
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/*
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* This fixups the register CCM_CSCMR1 write value.
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* The write/read/divider values of the aclk_podf field
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* of that register have the relationship described by
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* the following table:
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*
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* write value read value divider
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* 3b'000 3b'110 7
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* 3b'001 3b'111 8
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* 3b'010 3b'100 5
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* 3b'011 3b'101 6
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* 3b'100 3b'010 3
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* 3b'101 3b'011 4
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* 3b'110 3b'000 1
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* 3b'111 3b'001 2(default)
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*
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* That's why we do the xor operation below.
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*/
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#define CSCMR1_FIXUP 0x00600000
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void imx_cscmr1_fixup(u32 *val)
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{
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*val ^= CSCMR1_FIXUP;
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return;
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}
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