f9a5e6a27d
Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
319 lines
12 KiB
C
319 lines
12 KiB
C
/*
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* Copyright 2001 Mike Corrigan, IBM Corp
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/types.h>
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#include <linux/threads.h>
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#include <linux/module.h>
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#include <linux/bitops.h>
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#include <asm/processor.h>
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#include <asm/ptrace.h>
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#include <asm/abs_addr.h>
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#include <asm/lppaca.h>
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#include <asm/paca.h>
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#include <asm/iseries/lpar_map.h>
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#include <asm/iseries/it_lp_queue.h>
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#include <asm/iseries/alpaca.h>
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#include "naca.h"
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#include "vpd_areas.h"
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#include "spcomm_area.h"
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#include "ipl_parms.h"
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#include "processor_vpd.h"
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#include "release_data.h"
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#include "it_exp_vpd_panel.h"
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#include "it_lp_naca.h"
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/* The HvReleaseData is the root of the information shared between
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* the hypervisor and Linux.
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*/
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const struct HvReleaseData hvReleaseData = {
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.xDesc = 0xc8a5d9c4, /* "HvRD" ebcdic */
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.xSize = sizeof(struct HvReleaseData),
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.xVpdAreasPtrOffset = offsetof(struct naca_struct, xItVpdAreas),
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.xSlicNacaAddr = &naca, /* 64-bit Naca address */
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.xMsNucDataOffset = LPARMAP_PHYS,
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.xFlags = HVREL_TAGSINACTIVE /* tags inactive */
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/* 64 bit */
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/* shared processors */
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/* HMT allowed */
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| 6, /* TEMP: This allows non-GA driver */
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.xVrmIndex = 4, /* We are v5r2m0 */
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.xMinSupportedPlicVrmIndex = 3, /* v5r1m0 */
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.xMinCompatablePlicVrmIndex = 3, /* v5r1m0 */
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.xVrmName = { 0xd3, 0x89, 0x95, 0xa4, /* "Linux 2.4.64" ebcdic */
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0xa7, 0x40, 0xf2, 0x4b,
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0xf4, 0x4b, 0xf6, 0xf4 },
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};
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/*
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* The NACA. The first dword of the naca is required by the iSeries
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* hypervisor to point to itVpdAreas. The hypervisor finds the NACA
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* through the pointer in hvReleaseData.
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*/
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struct naca_struct naca = {
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.xItVpdAreas = &itVpdAreas,
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.xRamDisk = 0,
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.xRamDiskSize = 0,
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};
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struct ItLpRegSave {
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u32 xDesc; // Eye catcher "LpRS" ebcdic 000-003
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u16 xSize; // Size of this class 004-005
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u8 xInUse; // Area is live 006-007
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u8 xRsvd1[9]; // Reserved 007-00F
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u8 xFixedRegSave[352]; // Fixed Register Save Area 010-16F
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u32 xCTRL; // Control Register 170-173
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u32 xDEC; // Decrementer 174-177
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u32 xFPSCR; // FP Status and Control Reg 178-17B
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u32 xPVR; // Processor Version Number 17C-17F
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u64 xMMCR0; // Monitor Mode Control Reg 0 180-187
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u32 xPMC1; // Perf Monitor Counter 1 188-18B
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u32 xPMC2; // Perf Monitor Counter 2 18C-18F
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u32 xPMC3; // Perf Monitor Counter 3 190-193
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u32 xPMC4; // Perf Monitor Counter 4 194-197
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u32 xPIR; // Processor ID Reg 198-19B
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u32 xMMCR1; // Monitor Mode Control Reg 1 19C-19F
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u32 xMMCRA; // Monitor Mode Control Reg A 1A0-1A3
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u32 xPMC5; // Perf Monitor Counter 5 1A4-1A7
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u32 xPMC6; // Perf Monitor Counter 6 1A8-1AB
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u32 xPMC7; // Perf Monitor Counter 7 1AC-1AF
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u32 xPMC8; // Perf Monitor Counter 8 1B0-1B3
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u32 xTSC; // Thread Switch Control 1B4-1B7
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u32 xTST; // Thread Switch Timeout 1B8-1BB
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u32 xRsvd; // Reserved 1BC-1BF
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u64 xACCR; // Address Compare Control Reg 1C0-1C7
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u64 xIMR; // Instruction Match Register 1C8-1CF
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u64 xSDR1; // Storage Description Reg 1 1D0-1D7
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u64 xSPRG0; // Special Purpose Reg General0 1D8-1DF
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u64 xSPRG1; // Special Purpose Reg General1 1E0-1E7
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u64 xSPRG2; // Special Purpose Reg General2 1E8-1EF
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u64 xSPRG3; // Special Purpose Reg General3 1F0-1F7
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u64 xTB; // Time Base Register 1F8-1FF
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u64 xFPR[32]; // Floating Point Registers 200-2FF
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u64 xMSR; // Machine State Register 300-307
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u64 xNIA; // Next Instruction Address 308-30F
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u64 xDABR; // Data Address Breakpoint Reg 310-317
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u64 xIABR; // Inst Address Breakpoint Reg 318-31F
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u64 xHID0; // HW Implementation Dependent0 320-327
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u64 xHID4; // HW Implementation Dependent4 328-32F
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u64 xSCOMd; // SCON Data Reg (SPRG4) 330-337
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u64 xSCOMc; // SCON Command Reg (SPRG5) 338-33F
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u64 xSDAR; // Sample Data Address Register 340-347
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u64 xSIAR; // Sample Inst Address Register 348-34F
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u8 xRsvd3[176]; // Reserved 350-3FF
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};
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extern void system_reset_iSeries(void);
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extern void machine_check_iSeries(void);
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extern void data_access_iSeries(void);
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extern void instruction_access_iSeries(void);
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extern void hardware_interrupt_iSeries(void);
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extern void alignment_iSeries(void);
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extern void program_check_iSeries(void);
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extern void fp_unavailable_iSeries(void);
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extern void decrementer_iSeries(void);
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extern void trap_0a_iSeries(void);
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extern void trap_0b_iSeries(void);
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extern void system_call_iSeries(void);
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extern void single_step_iSeries(void);
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extern void trap_0e_iSeries(void);
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extern void performance_monitor_iSeries(void);
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extern void data_access_slb_iSeries(void);
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extern void instruction_access_slb_iSeries(void);
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struct ItLpNaca itLpNaca = {
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.xDesc = 0xd397d581, /* "LpNa" ebcdic */
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.xSize = 0x0400, /* size of ItLpNaca */
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.xIntHdlrOffset = 0x0300, /* offset to int array */
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.xMaxIntHdlrEntries = 19, /* # ents */
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.xPrimaryLpIndex = 0, /* Part # of primary */
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.xServiceLpIndex = 0, /* Part # of serv */
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.xLpIndex = 0, /* Part # of me */
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.xMaxLpQueues = 0, /* # of LP queues */
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.xLpQueueOffset = 0x100, /* offset of start of LP queues */
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.xPirEnvironMode = 0, /* Piranha stuff */
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.xPirConsoleMode = 0,
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.xPirDasdMode = 0,
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.flags = 0,
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.xSpVpdFormat = 0,
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.xIntProcRatio = 0,
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.xPlicVrmIndex = 0, /* VRM index of PLIC */
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.xMinSupportedSlicVrmInd = 0, /* min supported SLIC */
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.xMinCompatableSlicVrmInd = 0, /* min compat SLIC */
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.xLoadAreaAddr = 0, /* 64-bit addr of load area */
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.xLoadAreaChunks = 0, /* chunks for load area */
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.xPaseSysCallCRMask = 0, /* PASE mask */
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.xSlicSegmentTablePtr = 0, /* seg table */
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.xOldLpQueue = { 0 }, /* Old LP Queue */
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.xInterruptHdlr = {
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(u64)system_reset_iSeries, /* 0x100 System Reset */
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(u64)machine_check_iSeries, /* 0x200 Machine Check */
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(u64)data_access_iSeries, /* 0x300 Data Access */
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(u64)instruction_access_iSeries, /* 0x400 Instruction Access */
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(u64)hardware_interrupt_iSeries, /* 0x500 External */
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(u64)alignment_iSeries, /* 0x600 Alignment */
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(u64)program_check_iSeries, /* 0x700 Program Check */
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(u64)fp_unavailable_iSeries, /* 0x800 FP Unavailable */
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(u64)decrementer_iSeries, /* 0x900 Decrementer */
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(u64)trap_0a_iSeries, /* 0xa00 Trap 0A */
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(u64)trap_0b_iSeries, /* 0xb00 Trap 0B */
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(u64)system_call_iSeries, /* 0xc00 System Call */
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(u64)single_step_iSeries, /* 0xd00 Single Step */
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(u64)trap_0e_iSeries, /* 0xe00 Trap 0E */
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(u64)performance_monitor_iSeries,/* 0xf00 Performance Monitor */
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0, /* int 0x1000 */
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0, /* int 0x1010 */
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0, /* int 0x1020 CPU ctls */
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(u64)hardware_interrupt_iSeries, /* SC Ret Hdlr */
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(u64)data_access_slb_iSeries, /* 0x380 D-SLB */
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(u64)instruction_access_slb_iSeries /* 0x480 I-SLB */
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}
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};
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/* May be filled in by the hypervisor so cannot end up in the BSS */
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static struct ItIplParmsReal xItIplParmsReal __attribute__((__section__(".data")));
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/* May be filled in by the hypervisor so cannot end up in the BSS */
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struct ItExtVpdPanel xItExtVpdPanel __attribute__((__section__(".data")));
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#define maxPhysicalProcessors 32
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struct IoHriProcessorVpd xIoHriProcessorVpd[maxPhysicalProcessors] = {
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{
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.xInstCacheOperandSize = 32,
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.xDataCacheOperandSize = 32,
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.xProcFreq = 50000000,
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.xTimeBaseFreq = 50000000,
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.xPVR = 0x3600
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}
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};
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/* Space for Main Store Vpd 27,200 bytes */
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/* May be filled in by the hypervisor so cannot end up in the BSS */
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u64 xMsVpd[3400] __attribute__((__section__(".data")));
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/* Space for Recovery Log Buffer */
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/* May be filled in by the hypervisor so cannot end up in the BSS */
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static u64 xRecoveryLogBuffer[32] __attribute__((__section__(".data")));
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static const struct SpCommArea xSpCommArea = {
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.xDesc = 0xE2D7C3C2,
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.xFormat = 1,
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};
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static const struct ItLpRegSave iseries_reg_save[] = {
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[0 ... (NR_CPUS-1)] = {
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.xDesc = 0xd397d9e2, /* "LpRS" */
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.xSize = sizeof(struct ItLpRegSave),
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},
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};
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#define ALPACA_INIT(number) \
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{ \
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.lppaca_ptr = &lppaca[number], \
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.reg_save_ptr = &iseries_reg_save[number], \
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}
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const struct alpaca alpaca[] = {
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ALPACA_INIT( 0),
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#if NR_CPUS > 1
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ALPACA_INIT( 1), ALPACA_INIT( 2), ALPACA_INIT( 3),
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#if NR_CPUS > 4
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ALPACA_INIT( 4), ALPACA_INIT( 5), ALPACA_INIT( 6), ALPACA_INIT( 7),
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#if NR_CPUS > 8
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ALPACA_INIT( 8), ALPACA_INIT( 9), ALPACA_INIT(10), ALPACA_INIT(11),
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ALPACA_INIT(12), ALPACA_INIT(13), ALPACA_INIT(14), ALPACA_INIT(15),
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ALPACA_INIT(16), ALPACA_INIT(17), ALPACA_INIT(18), ALPACA_INIT(19),
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ALPACA_INIT(20), ALPACA_INIT(21), ALPACA_INIT(22), ALPACA_INIT(23),
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ALPACA_INIT(24), ALPACA_INIT(25), ALPACA_INIT(26), ALPACA_INIT(27),
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ALPACA_INIT(28), ALPACA_INIT(29), ALPACA_INIT(30), ALPACA_INIT(31),
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#if NR_CPUS > 32
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ALPACA_INIT(32), ALPACA_INIT(33), ALPACA_INIT(34), ALPACA_INIT(35),
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ALPACA_INIT(36), ALPACA_INIT(37), ALPACA_INIT(38), ALPACA_INIT(39),
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ALPACA_INIT(40), ALPACA_INIT(41), ALPACA_INIT(42), ALPACA_INIT(43),
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ALPACA_INIT(44), ALPACA_INIT(45), ALPACA_INIT(46), ALPACA_INIT(47),
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ALPACA_INIT(48), ALPACA_INIT(49), ALPACA_INIT(50), ALPACA_INIT(51),
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ALPACA_INIT(52), ALPACA_INIT(53), ALPACA_INIT(54), ALPACA_INIT(55),
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ALPACA_INIT(56), ALPACA_INIT(57), ALPACA_INIT(58), ALPACA_INIT(59),
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ALPACA_INIT(60), ALPACA_INIT(61), ALPACA_INIT(62), ALPACA_INIT(63),
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#endif
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#endif
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#endif
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#endif
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};
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/* The LparMap data is now located at offset 0x6000 in head.S
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* It was put there so that the HvReleaseData could address it
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* with a 32-bit offset as required by the iSeries hypervisor
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*
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* The Naca has a pointer to the ItVpdAreas. The hypervisor finds
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* the Naca via the HvReleaseData area. The HvReleaseData has the
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* offset into the Naca of the pointer to the ItVpdAreas.
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*/
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const struct ItVpdAreas itVpdAreas = {
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.xSlicDesc = 0xc9a3e5c1, /* "ItVA" */
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.xSlicSize = sizeof(struct ItVpdAreas),
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.xSlicVpdEntries = ItVpdMaxEntries, /* # VPD array entries */
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.xSlicDmaEntries = ItDmaMaxEntries, /* # DMA array entries */
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.xSlicMaxLogicalProcs = NR_CPUS * 2, /* Max logical procs */
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.xSlicMaxPhysicalProcs = maxPhysicalProcessors, /* Max physical procs */
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.xSlicDmaToksOffset = offsetof(struct ItVpdAreas, xPlicDmaToks),
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.xSlicVpdAdrsOffset = offsetof(struct ItVpdAreas, xSlicVpdAdrs),
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.xSlicDmaLensOffset = offsetof(struct ItVpdAreas, xPlicDmaLens),
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.xSlicVpdLensOffset = offsetof(struct ItVpdAreas, xSlicVpdLens),
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.xSlicMaxSlotLabels = 0, /* max slot labels */
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.xSlicMaxLpQueues = 1, /* max LP queues */
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.xPlicDmaLens = { 0 }, /* DMA lengths */
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.xPlicDmaToks = { 0 }, /* DMA tokens */
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.xSlicVpdLens = { /* VPD lengths */
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0,0,0, /* 0 - 2 */
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sizeof(xItExtVpdPanel), /* 3 Extended VPD */
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sizeof(struct alpaca), /* 4 length of (fake) Paca */
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0, /* 5 */
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sizeof(struct ItIplParmsReal),/* 6 length of IPL parms */
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26992, /* 7 length of MS VPD */
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0, /* 8 */
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sizeof(struct ItLpNaca),/* 9 length of LP Naca */
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0, /* 10 */
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256, /* 11 length of Recovery Log Buf */
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sizeof(struct SpCommArea), /* 12 length of SP Comm Area */
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0,0,0, /* 13 - 15 */
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sizeof(struct IoHriProcessorVpd),/* 16 length of Proc Vpd */
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0,0,0,0,0,0, /* 17 - 22 */
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sizeof(struct hvlpevent_queue), /* 23 length of Lp Queue */
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0,0 /* 24 - 25 */
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},
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.xSlicVpdAdrs = { /* VPD addresses */
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0,0,0, /* 0 - 2 */
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&xItExtVpdPanel, /* 3 Extended VPD */
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&alpaca[0], /* 4 first (fake) Paca */
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0, /* 5 */
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&xItIplParmsReal, /* 6 IPL parms */
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&xMsVpd, /* 7 MS Vpd */
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0, /* 8 */
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&itLpNaca, /* 9 LpNaca */
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0, /* 10 */
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&xRecoveryLogBuffer, /* 11 Recovery Log Buffer */
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&xSpCommArea, /* 12 SP Comm Area */
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0,0,0, /* 13 - 15 */
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&xIoHriProcessorVpd, /* 16 Proc Vpd */
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0,0,0,0,0,0, /* 17 - 22 */
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&hvlpevent_queue, /* 23 Lp Queue */
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0,0
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}
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};
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