06be2efaf4
This splits out a per-SoC IRQ range handling, so that the DB8500 and DB5500 SoC:s can reuse aproximately the same IRQ range with the largest span setting the roof. The same change is done for the boards, mutatis mutandis, with a new file for the U5500 board. Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
150 lines
6.5 KiB
C
150 lines
6.5 KiB
C
/*
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* Copyright (C) ST-Ericsson SA 2010
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*
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* Author: Rabin Vincent <rabin.vincent@stericsson.com>
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* License terms: GNU General Public License (GPL) version 2
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*/
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#ifndef __MACH_IRQS_DB8500_H
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#define __MACH_IRQS_DB8500_H
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#define IRQ_DB8500_MTU0 (IRQ_SHPI_START + 4)
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#define IRQ_DB8500_SPI2 (IRQ_SHPI_START + 6)
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#define IRQ_DB8500_PMU (IRQ_SHPI_START + 7)
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#define IRQ_DB8500_SPI0 (IRQ_SHPI_START + 8)
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#define IRQ_DB8500_RTT (IRQ_SHPI_START + 9)
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#define IRQ_DB8500_PKA (IRQ_SHPI_START + 10)
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#define IRQ_DB8500_UART0 (IRQ_SHPI_START + 11)
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#define IRQ_DB8500_I2C3 (IRQ_SHPI_START + 12)
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#define IRQ_DB8500_L2CC (IRQ_SHPI_START + 13)
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#define IRQ_DB8500_SSP0 (IRQ_SHPI_START + 14)
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#define IRQ_DB8500_CRYP1 (IRQ_SHPI_START + 15)
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#define IRQ_DB8500_MSP1_RX (IRQ_SHPI_START + 16)
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#define IRQ_DB8500_MTU1 (IRQ_SHPI_START + 17)
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#define IRQ_DB8500_RTC (IRQ_SHPI_START + 18)
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#define IRQ_DB8500_UART1 (IRQ_SHPI_START + 19)
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#define IRQ_DB8500_USB_WAKEUP (IRQ_SHPI_START + 20)
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#define IRQ_DB8500_I2C0 (IRQ_SHPI_START + 21)
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#define IRQ_DB8500_I2C1 (IRQ_SHPI_START + 22)
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#define IRQ_DB8500_USBOTG (IRQ_SHPI_START + 23)
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#define IRQ_DB8500_DMA_SECURE (IRQ_SHPI_START + 24)
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#define IRQ_DB8500_DMA (IRQ_SHPI_START + 25)
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#define IRQ_DB8500_UART2 (IRQ_SHPI_START + 26)
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#define IRQ_DB8500_ICN_PMU1 (IRQ_SHPI_START + 27)
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#define IRQ_DB8500_ICN_PMU2 (IRQ_SHPI_START + 28)
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#define IRQ_DB8500_HSIR_EXCEP (IRQ_SHPI_START + 29)
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#define IRQ_DB8500_MSP0 (IRQ_SHPI_START + 31)
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#define IRQ_DB8500_HSIR_CH0_OVRRUN (IRQ_SHPI_START + 32)
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#define IRQ_DB8500_HSIR_CH1_OVRRUN (IRQ_SHPI_START + 33)
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#define IRQ_DB8500_HSIR_CH2_OVRRUN (IRQ_SHPI_START + 34)
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#define IRQ_DB8500_HSIR_CH3_OVRRUN (IRQ_SHPI_START + 35)
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#define IRQ_DB8500_HSIR_CH4_OVRRUN (IRQ_SHPI_START + 36)
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#define IRQ_DB8500_HSIR_CH5_OVRRUN (IRQ_SHPI_START + 37)
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#define IRQ_DB8500_HSIR_CH6_OVRRUN (IRQ_SHPI_START + 38)
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#define IRQ_DB8500_HSIR_CH7_OVRRUN (IRQ_SHPI_START + 39)
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#define IRQ_DB8500_AB8500 (IRQ_SHPI_START + 40)
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#define IRQ_DB8500_SDMMC2 (IRQ_SHPI_START + 41)
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#define IRQ_DB8500_SIA (IRQ_SHPI_START + 42)
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#define IRQ_DB8500_SIA2 (IRQ_SHPI_START + 43)
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#define IRQ_DB8500_SVA (IRQ_SHPI_START + 44)
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#define IRQ_DB8500_SVA2 (IRQ_SHPI_START + 45)
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#define IRQ_DB8500_PRCMU0 (IRQ_SHPI_START + 46)
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#define IRQ_DB8500_PRCMU1 (IRQ_SHPI_START + 47)
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#define IRQ_DB8500_DISP (IRQ_SHPI_START + 48)
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#define IRQ_DB8500_SPI3 (IRQ_SHPI_START + 49)
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#define IRQ_DB8500_SDMMC1 (IRQ_SHPI_START + 50)
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#define IRQ_DB8500_I2C4 (IRQ_SHPI_START + 51)
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#define IRQ_DB8500_SSP1 (IRQ_SHPI_START + 52)
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#define IRQ_DB8500_SKE (IRQ_SHPI_START + 53)
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#define IRQ_DB8500_KB (IRQ_SHPI_START + 54)
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#define IRQ_DB8500_I2C2 (IRQ_SHPI_START + 55)
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#define IRQ_DB8500_B2R2 (IRQ_SHPI_START + 56)
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#define IRQ_DB8500_CRYP0 (IRQ_SHPI_START + 57)
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#define IRQ_DB8500_SDMMC3 (IRQ_SHPI_START + 59)
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#define IRQ_DB8500_SDMMC0 (IRQ_SHPI_START + 60)
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#define IRQ_DB8500_HSEM (IRQ_SHPI_START + 61)
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#define IRQ_DB8500_MSP1 (IRQ_SHPI_START + 62)
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#define IRQ_DB8500_SBAG (IRQ_SHPI_START + 63)
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#define IRQ_DB8500_SPI1 (IRQ_SHPI_START + 96)
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#define IRQ_DB8500_SRPTIMER (IRQ_SHPI_START + 97)
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#define IRQ_DB8500_MSP2 (IRQ_SHPI_START + 98)
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#define IRQ_DB8500_SDMMC4 (IRQ_SHPI_START + 99)
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#define IRQ_DB8500_SDMMC5 (IRQ_SHPI_START + 100)
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#define IRQ_DB8500_HSIRD0 (IRQ_SHPI_START + 104)
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#define IRQ_DB8500_HSIRD1 (IRQ_SHPI_START + 105)
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#define IRQ_DB8500_HSITD0 (IRQ_SHPI_START + 106)
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#define IRQ_DB8500_HSITD1 (IRQ_SHPI_START + 107)
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#define IRQ_DB8500_CTI0 (IRQ_SHPI_START + 108)
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#define IRQ_DB8500_CTI1 (IRQ_SHPI_START + 109)
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#define IRQ_DB8500_ICN_ERR (IRQ_SHPI_START + 110)
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#define IRQ_DB8500_MALI_PPMMU (IRQ_SHPI_START + 112)
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#define IRQ_DB8500_MALI_PP (IRQ_SHPI_START + 113)
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#define IRQ_DB8500_MALI_GPMMU (IRQ_SHPI_START + 114)
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#define IRQ_DB8500_MALI_GP (IRQ_SHPI_START + 115)
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#define IRQ_DB8500_MALI (IRQ_SHPI_START + 116)
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#define IRQ_DB8500_PRCMU_SEM (IRQ_SHPI_START + 118)
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#define IRQ_DB8500_GPIO0 (IRQ_SHPI_START + 119)
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#define IRQ_DB8500_GPIO1 (IRQ_SHPI_START + 120)
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#define IRQ_DB8500_GPIO2 (IRQ_SHPI_START + 121)
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#define IRQ_DB8500_GPIO3 (IRQ_SHPI_START + 122)
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#define IRQ_DB8500_GPIO4 (IRQ_SHPI_START + 123)
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#define IRQ_DB8500_GPIO5 (IRQ_SHPI_START + 124)
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#define IRQ_DB8500_GPIO6 (IRQ_SHPI_START + 125)
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#define IRQ_DB8500_GPIO7 (IRQ_SHPI_START + 126)
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#define IRQ_DB8500_GPIO8 (IRQ_SHPI_START + 127)
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#define IRQ_CA_WAKE_REQ_ED (IRQ_SHPI_START + 71)
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#define IRQ_AC_READ_NOTIFICATION_0_ED (IRQ_SHPI_START + 66)
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#define IRQ_AC_READ_NOTIFICATION_1_ED (IRQ_SHPI_START + 64)
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#define IRQ_CA_MSG_PEND_NOTIFICATION_0_ED (IRQ_SHPI_START + 67)
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#define IRQ_CA_MSG_PEND_NOTIFICATION_1_ED (IRQ_SHPI_START + 65)
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#define IRQ_CA_WAKE_REQ_V1 (IRQ_SHPI_START + 83)
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#define IRQ_AC_READ_NOTIFICATION_0_V1 (IRQ_SHPI_START + 78)
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#define IRQ_AC_READ_NOTIFICATION_1_V1 (IRQ_SHPI_START + 76)
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#define IRQ_CA_MSG_PEND_NOTIFICATION_0_V1 (IRQ_SHPI_START + 79)
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#define IRQ_CA_MSG_PEND_NOTIFICATION_1_V1 (IRQ_SHPI_START + 77)
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#ifdef CONFIG_UX500_SOC_DB8500
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/* Virtual interrupts corresponding to the PRCMU wakeups. */
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#define IRQ_PRCMU_BASE IRQ_SOC_START
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#define NUM_PRCMU_WAKEUPS (IRQ_PRCMU_END - IRQ_PRCMU_BASE)
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#define IRQ_PRCMU_RTC (IRQ_PRCMU_BASE)
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#define IRQ_PRCMU_RTT0 (IRQ_PRCMU_BASE + 1)
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#define IRQ_PRCMU_RTT1 (IRQ_PRCMU_BASE + 2)
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#define IRQ_PRCMU_HSI0 (IRQ_PRCMU_BASE + 3)
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#define IRQ_PRCMU_HSI1 (IRQ_PRCMU_BASE + 4)
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#define IRQ_PRCMU_CA_WAKE (IRQ_PRCMU_BASE + 5)
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#define IRQ_PRCMU_USB (IRQ_PRCMU_BASE + 6)
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#define IRQ_PRCMU_ABB (IRQ_PRCMU_BASE + 7)
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#define IRQ_PRCMU_ABB_FIFO (IRQ_PRCMU_BASE + 8)
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#define IRQ_PRCMU_ARM (IRQ_PRCMU_BASE + 9)
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#define IRQ_PRCMU_MODEM_SW_RESET_REQ (IRQ_PRCMU_BASE + 10)
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#define IRQ_PRCMU_GPIO0 (IRQ_PRCMU_BASE + 11)
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#define IRQ_PRCMU_GPIO1 (IRQ_PRCMU_BASE + 12)
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#define IRQ_PRCMU_GPIO2 (IRQ_PRCMU_BASE + 13)
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#define IRQ_PRCMU_GPIO3 (IRQ_PRCMU_BASE + 14)
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#define IRQ_PRCMU_GPIO4 (IRQ_PRCMU_BASE + 15)
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#define IRQ_PRCMU_GPIO5 (IRQ_PRCMU_BASE + 16)
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#define IRQ_PRCMU_GPIO6 (IRQ_PRCMU_BASE + 17)
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#define IRQ_PRCMU_GPIO7 (IRQ_PRCMU_BASE + 18)
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#define IRQ_PRCMU_GPIO8 (IRQ_PRCMU_BASE + 19)
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#define IRQ_PRCMU_CA_SLEEP (IRQ_PRCMU_BASE + 20)
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#define IRQ_PRCMU_HOTMON_LOW (IRQ_PRCMU_BASE + 21)
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#define IRQ_PRCMU_HOTMON_HIGH (IRQ_PRCMU_BASE + 22)
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#define IRQ_PRCMU_END (IRQ_PRCMU_BASE + 23)
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/*
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* We may have several SoCs, but only one will run at a
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* time, so the one with most IRQs will bump this ahead,
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* but the IRQ_SOC_START remains the same for either SoC.
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*/
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#if IRQ_SOC_END < IRQ_PRCMU_END
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#undef IRQ_SOC_END
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#define IRQ_SOC_END IRQ_PRCMU_END
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#endif
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#endif /* CONFIG_UX500_SOC_DB8500 */
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#endif
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