 10d8935f46
			
		
	
	
	10d8935f46
	
	
	
		
			
			viresh.kumar@st.com email-id doesn't exist anymore as I have left the company. Replace ST's id with viresh.linux@gmail.com. It also updates .mailmap file to fix address for 'git shortlog' Signed-off-by: Viresh Kumar <viresh.linux@gmail.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
		
			
				
	
	
		
			128 lines
		
	
	
	
		
			3.4 KiB
			
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			128 lines
		
	
	
	
		
			3.4 KiB
			
		
	
	
	
		
			C
		
	
	
	
	
	
| /*
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|  * arch/arm/mach-spear13xx/include/mach/dma.h
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|  *
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|  * DMA information for SPEAr13xx machine family
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|  *
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|  * Copyright (C) 2012 ST Microelectronics
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|  * Viresh Kumar <viresh.linux@gmail.com>
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|  *
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|  * This file is licensed under the terms of the GNU General Public
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|  * License version 2. This program is licensed "as is" without any
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|  * warranty of any kind, whether express or implied.
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|  */
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| 
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| #ifndef __MACH_DMA_H
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| #define __MACH_DMA_H
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| 
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| /* request id of all the peripherals */
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| enum dma_master_info {
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| 	/* Accessible from only one master */
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| 	DMA_MASTER_MCIF = 0,
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| 	DMA_MASTER_FSMC = 1,
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| 	/* Accessible from both 0 & 1 */
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| 	DMA_MASTER_MEMORY = 0,
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| 	DMA_MASTER_ADC = 0,
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| 	DMA_MASTER_UART0 = 0,
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| 	DMA_MASTER_SSP0 = 0,
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| 	DMA_MASTER_I2C0 = 0,
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| 
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| #ifdef CONFIG_MACH_SPEAR1310
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| 	/* Accessible from only one master */
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| 	SPEAR1310_DMA_MASTER_JPEG = 1,
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| 
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| 	/* Accessible from both 0 & 1 */
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| 	SPEAR1310_DMA_MASTER_I2S = 0,
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| 	SPEAR1310_DMA_MASTER_UART1 = 0,
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| 	SPEAR1310_DMA_MASTER_UART2 = 0,
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| 	SPEAR1310_DMA_MASTER_UART3 = 0,
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| 	SPEAR1310_DMA_MASTER_UART4 = 0,
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| 	SPEAR1310_DMA_MASTER_UART5 = 0,
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| 	SPEAR1310_DMA_MASTER_I2C1 = 0,
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| 	SPEAR1310_DMA_MASTER_I2C2 = 0,
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| 	SPEAR1310_DMA_MASTER_I2C3 = 0,
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| 	SPEAR1310_DMA_MASTER_I2C4 = 0,
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| 	SPEAR1310_DMA_MASTER_I2C5 = 0,
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| 	SPEAR1310_DMA_MASTER_I2C6 = 0,
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| 	SPEAR1310_DMA_MASTER_I2C7 = 0,
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| 	SPEAR1310_DMA_MASTER_SSP1 = 0,
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| #endif
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| 
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| #ifdef CONFIG_MACH_SPEAR1340
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| 	/* Accessible from only one master */
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| 	SPEAR1340_DMA_MASTER_I2S_PLAY = 1,
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| 	SPEAR1340_DMA_MASTER_I2S_REC = 1,
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| 	SPEAR1340_DMA_MASTER_I2C1 = 1,
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| 	SPEAR1340_DMA_MASTER_UART1 = 1,
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| 
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| 	/* following are accessible from both master 0 & 1 */
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| 	SPEAR1340_DMA_MASTER_SPDIF = 0,
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| 	SPEAR1340_DMA_MASTER_CAM = 1,
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| 	SPEAR1340_DMA_MASTER_VIDEO_IN = 0,
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| 	SPEAR1340_DMA_MASTER_MALI = 0,
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| #endif
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| };
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| 
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| enum request_id {
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| 	DMA_REQ_ADC = 0,
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| 	DMA_REQ_SSP0_TX = 4,
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| 	DMA_REQ_SSP0_RX = 5,
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| 	DMA_REQ_UART0_TX = 6,
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| 	DMA_REQ_UART0_RX = 7,
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| 	DMA_REQ_I2C0_TX = 8,
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| 	DMA_REQ_I2C0_RX = 9,
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| 
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| #ifdef CONFIG_MACH_SPEAR1310
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| 	SPEAR1310_DMA_REQ_FROM_JPEG = 2,
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| 	SPEAR1310_DMA_REQ_TO_JPEG = 3,
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| 	SPEAR1310_DMA_REQ_I2S_TX = 10,
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| 	SPEAR1310_DMA_REQ_I2S_RX = 11,
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| 
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| 	SPEAR1310_DMA_REQ_I2C1_RX = 0,
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| 	SPEAR1310_DMA_REQ_I2C1_TX = 1,
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| 	SPEAR1310_DMA_REQ_I2C2_RX = 2,
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| 	SPEAR1310_DMA_REQ_I2C2_TX = 3,
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| 	SPEAR1310_DMA_REQ_I2C3_RX = 4,
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| 	SPEAR1310_DMA_REQ_I2C3_TX = 5,
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| 	SPEAR1310_DMA_REQ_I2C4_RX = 6,
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| 	SPEAR1310_DMA_REQ_I2C4_TX = 7,
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| 	SPEAR1310_DMA_REQ_I2C5_RX = 8,
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| 	SPEAR1310_DMA_REQ_I2C5_TX = 9,
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| 	SPEAR1310_DMA_REQ_I2C6_RX = 10,
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| 	SPEAR1310_DMA_REQ_I2C6_TX = 11,
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| 	SPEAR1310_DMA_REQ_UART1_RX = 12,
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| 	SPEAR1310_DMA_REQ_UART1_TX = 13,
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| 	SPEAR1310_DMA_REQ_UART2_RX = 14,
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| 	SPEAR1310_DMA_REQ_UART2_TX = 15,
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| 	SPEAR1310_DMA_REQ_UART5_RX = 16,
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| 	SPEAR1310_DMA_REQ_UART5_TX = 17,
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| 	SPEAR1310_DMA_REQ_SSP1_RX = 18,
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| 	SPEAR1310_DMA_REQ_SSP1_TX = 19,
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| 	SPEAR1310_DMA_REQ_I2C7_RX = 20,
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| 	SPEAR1310_DMA_REQ_I2C7_TX = 21,
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| 	SPEAR1310_DMA_REQ_UART3_RX = 28,
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| 	SPEAR1310_DMA_REQ_UART3_TX = 29,
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| 	SPEAR1310_DMA_REQ_UART4_RX = 30,
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| 	SPEAR1310_DMA_REQ_UART4_TX = 31,
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| #endif
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| 
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| #ifdef CONFIG_MACH_SPEAR1340
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| 	SPEAR1340_DMA_REQ_SPDIF_TX = 2,
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| 	SPEAR1340_DMA_REQ_SPDIF_RX = 3,
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| 	SPEAR1340_DMA_REQ_I2S_TX = 10,
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| 	SPEAR1340_DMA_REQ_I2S_RX = 11,
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| 	SPEAR1340_DMA_REQ_UART1_TX = 12,
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| 	SPEAR1340_DMA_REQ_UART1_RX = 13,
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| 	SPEAR1340_DMA_REQ_I2C1_TX = 14,
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| 	SPEAR1340_DMA_REQ_I2C1_RX = 15,
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| 	SPEAR1340_DMA_REQ_CAM0_EVEN = 0,
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| 	SPEAR1340_DMA_REQ_CAM0_ODD = 1,
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| 	SPEAR1340_DMA_REQ_CAM1_EVEN = 2,
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| 	SPEAR1340_DMA_REQ_CAM1_ODD = 3,
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| 	SPEAR1340_DMA_REQ_CAM2_EVEN = 4,
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| 	SPEAR1340_DMA_REQ_CAM2_ODD = 5,
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| 	SPEAR1340_DMA_REQ_CAM3_EVEN = 6,
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| 	SPEAR1340_DMA_REQ_CAM3_ODD = 7,
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| #endif
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| };
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| 
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| #endif /* __MACH_DMA_H */
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