6bb27d7349
Now that the only field in struct sys_timer is .init, delete the struct, and replace the machine descriptor .timer field with the initialization function itself. This will enable moving timer drivers into drivers/clocksource without having to place a public prototype of each struct sys_timer object into include/linux; the intent is to create a single of_clocksource_init() function that determines which timer driver to initialize by scanning the device dtree, much like the proposed irqchip_init() at: http://www.spinics.net/lists/arm-kernel/msg203686.html Includes mach-omap2 fixes from Igor Grinberg. Tested-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Stephen Warren <swarren@nvidia.com>
189 lines
4.9 KiB
C
189 lines
4.9 KiB
C
/*
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* arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
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*
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* Marvell Orion-VoIP GE Reference Design Setup
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/gpio.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/pci.h>
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#include <linux/irq.h>
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#include <linux/mtd/physmap.h>
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#include <linux/mv643xx_eth.h>
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#include <linux/ethtool.h>
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#include <linux/i2c.h>
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#include <net/dsa.h>
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#include <asm/mach-types.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/pci.h>
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#include <mach/orion5x.h>
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#include "common.h"
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#include "mpp.h"
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/*****************************************************************************
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* RD-88F5181L GE Info
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****************************************************************************/
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/*
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* 16M NOR flash Device bus boot chip select
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*/
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#define RD88F5181L_GE_NOR_BOOT_BASE 0xff000000
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#define RD88F5181L_GE_NOR_BOOT_SIZE SZ_16M
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/*****************************************************************************
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* 16M NOR Flash on Device bus Boot chip select
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****************************************************************************/
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static struct physmap_flash_data rd88f5181l_ge_nor_boot_flash_data = {
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.width = 1,
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};
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static struct resource rd88f5181l_ge_nor_boot_flash_resource = {
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.flags = IORESOURCE_MEM,
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.start = RD88F5181L_GE_NOR_BOOT_BASE,
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.end = RD88F5181L_GE_NOR_BOOT_BASE +
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RD88F5181L_GE_NOR_BOOT_SIZE - 1,
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};
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static struct platform_device rd88f5181l_ge_nor_boot_flash = {
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.name = "physmap-flash",
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.id = 0,
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.dev = {
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.platform_data = &rd88f5181l_ge_nor_boot_flash_data,
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},
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.num_resources = 1,
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.resource = &rd88f5181l_ge_nor_boot_flash_resource,
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};
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/*****************************************************************************
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* General Setup
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****************************************************************************/
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static unsigned int rd88f5181l_ge_mpp_modes[] __initdata = {
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MPP0_GPIO, /* LED1 */
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MPP1_GPIO, /* LED5 */
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MPP2_GPIO, /* LED4 */
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MPP3_GPIO, /* LED3 */
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MPP4_GPIO, /* PCI_intA */
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MPP5_GPIO, /* RTC interrupt */
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MPP6_PCI_CLK, /* CPU PCI refclk */
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MPP7_PCI_CLK, /* PCI/PCIe refclk */
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MPP8_GPIO, /* 88e6131 interrupt */
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MPP9_GPIO, /* GE_RXERR */
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MPP10_GPIO, /* PCI_intB */
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MPP11_GPIO, /* LED2 */
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MPP12_GIGE, /* GE_TXD[4] */
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MPP13_GIGE, /* GE_TXD[5] */
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MPP14_GIGE, /* GE_TXD[6] */
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MPP15_GIGE, /* GE_TXD[7] */
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MPP16_GIGE, /* GE_RXD[4] */
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MPP17_GIGE, /* GE_RXD[5] */
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MPP18_GIGE, /* GE_RXD[6] */
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MPP19_GIGE, /* GE_RXD[7] */
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0,
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};
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static struct mv643xx_eth_platform_data rd88f5181l_ge_eth_data = {
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.phy_addr = MV643XX_ETH_PHY_NONE,
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.speed = SPEED_1000,
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.duplex = DUPLEX_FULL,
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};
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static struct dsa_chip_data rd88f5181l_ge_switch_chip_data = {
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.port_names[0] = "lan2",
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.port_names[1] = "lan1",
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.port_names[2] = "wan",
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.port_names[3] = "cpu",
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.port_names[5] = "lan4",
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.port_names[7] = "lan3",
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};
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static struct dsa_platform_data rd88f5181l_ge_switch_plat_data = {
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.nr_chips = 1,
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.chip = &rd88f5181l_ge_switch_chip_data,
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};
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static struct i2c_board_info __initdata rd88f5181l_ge_i2c_rtc = {
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I2C_BOARD_INFO("ds1338", 0x68),
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};
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static void __init rd88f5181l_ge_init(void)
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{
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/*
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* Setup basic Orion functions. Need to be called early.
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*/
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orion5x_init();
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orion5x_mpp_conf(rd88f5181l_ge_mpp_modes);
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/*
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* Configure peripherals.
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*/
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orion5x_ehci0_init();
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orion5x_eth_init(&rd88f5181l_ge_eth_data);
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orion5x_eth_switch_init(&rd88f5181l_ge_switch_plat_data,
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gpio_to_irq(8));
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orion5x_i2c_init();
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orion5x_uart0_init();
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orion5x_setup_dev_boot_win(RD88F5181L_GE_NOR_BOOT_BASE,
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RD88F5181L_GE_NOR_BOOT_SIZE);
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platform_device_register(&rd88f5181l_ge_nor_boot_flash);
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i2c_register_board_info(0, &rd88f5181l_ge_i2c_rtc, 1);
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}
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static int __init
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rd88f5181l_ge_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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{
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int irq;
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/*
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* Check for devices with hard-wired IRQs.
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*/
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irq = orion5x_pci_map_irq(dev, slot, pin);
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if (irq != -1)
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return irq;
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/*
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* Cardbus slot.
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*/
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if (pin == 1)
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return gpio_to_irq(4);
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else
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return gpio_to_irq(10);
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}
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static struct hw_pci rd88f5181l_ge_pci __initdata = {
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.nr_controllers = 2,
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.setup = orion5x_pci_sys_setup,
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.scan = orion5x_pci_sys_scan_bus,
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.map_irq = rd88f5181l_ge_pci_map_irq,
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};
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static int __init rd88f5181l_ge_pci_init(void)
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{
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if (machine_is_rd88f5181l_ge()) {
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orion5x_pci_set_cardbus_mode();
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pci_common_init(&rd88f5181l_ge_pci);
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}
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return 0;
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}
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subsys_initcall(rd88f5181l_ge_pci_init);
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MACHINE_START(RD88F5181L_GE, "Marvell Orion-VoIP GE Reference Design")
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/* Maintainer: Lennert Buytenhek <buytenh@marvell.com> */
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.atag_offset = 0x100,
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.init_machine = rd88f5181l_ge_init,
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.map_io = orion5x_map_io,
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.init_early = orion5x_init_early,
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.init_irq = orion5x_init_irq,
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.init_time = orion5x_timer_init,
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.fixup = tag_fixup_mem32,
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.restart = orion5x_restart,
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MACHINE_END
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