 21ccdd31e9
			
		
	
	
	21ccdd31e9
	
	
	
		
			
			In the MPIC U3 MSI code, we call u3msi_compose_msi_msg() once for each MSI. This is overkill, as the address is per pci device, not per MSI. So setup the address once, and just set the data per MSI. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
		
			
				
	
	
		
			174 lines
		
	
	
	
		
			3.8 KiB
			
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			174 lines
		
	
	
	
		
			3.8 KiB
			
		
	
	
	
		
			C
		
	
	
	
	
	
| /*
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|  * Copyright 2006, Segher Boessenkool, IBM Corporation.
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|  * Copyright 2006-2007, Michael Ellerman, IBM Corporation.
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|  *
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|  * This program is free software; you can redistribute it and/or
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|  * modify it under the terms of the GNU General Public License
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|  * as published by the Free Software Foundation; version 2 of the
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|  * License.
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|  *
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|  */
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| 
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| #include <linux/irq.h>
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| #include <linux/bootmem.h>
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| #include <linux/msi.h>
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| #include <asm/mpic.h>
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| #include <asm/prom.h>
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| #include <asm/hw_irq.h>
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| #include <asm/ppc-pci.h>
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| 
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| #include "mpic.h"
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| 
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| /* A bit ugly, can we get this from the pci_dev somehow? */
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| static struct mpic *msi_mpic;
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| 
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| static void mpic_u3msi_mask_irq(unsigned int irq)
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| {
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| 	mask_msi_irq(irq);
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| 	mpic_mask_irq(irq);
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| }
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| 
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| static void mpic_u3msi_unmask_irq(unsigned int irq)
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| {
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| 	mpic_unmask_irq(irq);
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| 	unmask_msi_irq(irq);
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| }
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| 
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| static struct irq_chip mpic_u3msi_chip = {
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| 	.shutdown	= mpic_u3msi_mask_irq,
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| 	.mask		= mpic_u3msi_mask_irq,
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| 	.unmask		= mpic_u3msi_unmask_irq,
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| 	.eoi		= mpic_end_irq,
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| 	.set_type	= mpic_set_irq_type,
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| 	.set_affinity	= mpic_set_affinity,
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| 	.typename	= "MPIC-U3MSI",
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| };
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| 
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| static u64 read_ht_magic_addr(struct pci_dev *pdev, unsigned int pos)
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| {
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| 	u8 flags;
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| 	u32 tmp;
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| 	u64 addr;
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| 
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| 	pci_read_config_byte(pdev, pos + HT_MSI_FLAGS, &flags);
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| 
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| 	if (flags & HT_MSI_FLAGS_FIXED)
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| 		return HT_MSI_FIXED_ADDR;
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| 
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| 	pci_read_config_dword(pdev, pos + HT_MSI_ADDR_LO, &tmp);
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| 	addr = tmp & HT_MSI_ADDR_LO_MASK;
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| 	pci_read_config_dword(pdev, pos + HT_MSI_ADDR_HI, &tmp);
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| 	addr = addr | ((u64)tmp << 32);
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| 
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| 	return addr;
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| }
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| 
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| static u64 find_ht_magic_addr(struct pci_dev *pdev)
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| {
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| 	struct pci_bus *bus;
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| 	unsigned int pos;
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| 
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| 	for (bus = pdev->bus; bus; bus = bus->parent) {
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| 		pos = pci_find_ht_capability(bus->self, HT_CAPTYPE_MSI_MAPPING);
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| 		if (pos)
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| 			return read_ht_magic_addr(bus->self, pos);
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| 	}
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| 
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| 	return 0;
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| }
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| 
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| static int u3msi_msi_check_device(struct pci_dev *pdev, int nvec, int type)
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| {
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| 	if (type == PCI_CAP_ID_MSIX)
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| 		pr_debug("u3msi: MSI-X untested, trying anyway.\n");
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| 
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| 	/* If we can't find a magic address then MSI ain't gonna work */
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| 	if (find_ht_magic_addr(pdev) == 0) {
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| 		pr_debug("u3msi: no magic address found for %s\n",
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| 			 pci_name(pdev));
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| 		return -ENXIO;
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| 	}
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| 
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| 	return 0;
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| }
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| 
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| static void u3msi_teardown_msi_irqs(struct pci_dev *pdev)
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| {
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| 	struct msi_desc *entry;
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| 
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|         list_for_each_entry(entry, &pdev->msi_list, list) {
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| 		if (entry->irq == NO_IRQ)
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| 			continue;
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| 
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| 		set_irq_msi(entry->irq, NULL);
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| 		mpic_msi_free_hwirqs(msi_mpic, virq_to_hw(entry->irq), 1);
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| 		irq_dispose_mapping(entry->irq);
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| 	}
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| 
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| 	return;
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| }
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| 
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| static int u3msi_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
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| {
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| 	irq_hw_number_t hwirq;
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| 	unsigned int virq;
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| 	struct msi_desc *entry;
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| 	struct msi_msg msg;
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| 	u64 addr;
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| 
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| 	addr = find_ht_magic_addr(pdev);
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| 	msg.address_lo = addr & 0xFFFFFFFF;
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| 	msg.address_hi = addr >> 32;
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| 
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| 	list_for_each_entry(entry, &pdev->msi_list, list) {
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| 		hwirq = mpic_msi_alloc_hwirqs(msi_mpic, 1);
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| 		if (hwirq < 0) {
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| 			pr_debug("u3msi: failed allocating hwirq\n");
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| 			return hwirq;
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| 		}
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| 
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| 		virq = irq_create_mapping(msi_mpic->irqhost, hwirq);
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| 		if (virq == NO_IRQ) {
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| 			pr_debug("u3msi: failed mapping hwirq 0x%lx\n", hwirq);
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| 			mpic_msi_free_hwirqs(msi_mpic, hwirq, 1);
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| 			return -ENOSPC;
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| 		}
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| 
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| 		set_irq_msi(virq, entry);
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| 		set_irq_chip(virq, &mpic_u3msi_chip);
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| 		set_irq_type(virq, IRQ_TYPE_EDGE_RISING);
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| 
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| 		pr_debug("u3msi: allocated virq 0x%x (hw 0x%lx) addr 0x%lx\n",
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| 			  virq, hwirq, addr);
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| 
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| 		msg.data = hwirq;
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| 		write_msi_msg(virq, &msg);
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| 
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| 		hwirq++;
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| 	}
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| 
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| 	return 0;
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| }
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| 
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| int mpic_u3msi_init(struct mpic *mpic)
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| {
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| 	int rc;
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| 
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| 	rc = mpic_msi_init_allocator(mpic);
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| 	if (rc) {
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| 		pr_debug("u3msi: Error allocating bitmap!\n");
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| 		return rc;
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| 	}
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| 
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| 	pr_debug("u3msi: Registering MPIC U3 MSI callbacks.\n");
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| 
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| 	BUG_ON(msi_mpic);
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| 	msi_mpic = mpic;
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| 
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| 	WARN_ON(ppc_md.setup_msi_irqs);
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| 	ppc_md.setup_msi_irqs = u3msi_setup_msi_irqs;
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| 	ppc_md.teardown_msi_irqs = u3msi_teardown_msi_irqs;
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| 	ppc_md.msi_check_device = u3msi_msi_check_device;
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| 
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| 	return 0;
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| }
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