41195d236e
ARC common code to enable a SMP system + ISS provided SMP extensions. ARC700 natively lacks SMP support, hence some of the core features are are only enabled if SoCs have the necessary h/w pixie-dust. This includes: -Inter Processor Interrupts (IPI) -Cache coherency -load-locked/store-conditional ... The low level exception handling would be completely broken in SMP because we don't have hardware assisted stack switching. Thus a fair bit of this code is repurposing the MMU_SCRATCH reg for event handler prologues to keep them re-entrant. Many thanks to Rajeshwar Ranga for his initial "major" contributions to SMP Port (back in 2008), and to Noam Camus and Gilad Ben-Yossef for help with resurrecting that in 3.2 kernel (2012). Note that this platform code is again singleton design pattern - so multiple SMP platforms won't build at the moment - this deficiency is addressed in subsequent patches within this series. Signed-off-by: Vineet Gupta <vgupta@synopsys.com> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Rajeshwar Ranga <rajeshwar.ranga@gmail.com> Cc: Noam Camus <noamc@ezchip.com> Cc: Gilad Ben-Yossef <gilad@benyossef.com>
111 lines
2.9 KiB
ArmAsm
111 lines
2.9 KiB
ArmAsm
/*
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* ARC CPU startup Code
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*
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* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Vineetg: Dec 2007
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* -Check if we are running on Simulator or on real hardware
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* to skip certain things during boot on simulator
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*/
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#include <asm/asm-offsets.h>
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#include <asm/entry.h>
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#include <linux/linkage.h>
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#include <asm/arcregs.h>
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.cpu A7
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.section .init.text, "ax",@progbits
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.type stext, @function
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.globl stext
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stext:
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;-------------------------------------------------------------------
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; Don't clobber r0-r4 yet. It might have bootloader provided info
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;-------------------------------------------------------------------
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#ifdef CONFIG_SMP
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; Only Boot (Master) proceeds. Others wait in platform dependent way
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; IDENTITY Reg [ 3 2 1 0 ]
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; (cpu-id) ^^^ => Zero for UP ARC700
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; => #Core-ID if SMP (Master 0)
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GET_CPU_ID r5
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cmp r5, 0
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jnz arc_platform_smp_wait_to_boot
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#endif
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; Clear BSS before updating any globals
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; XXX: use ZOL here
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mov r5, __bss_start
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mov r6, __bss_stop
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1:
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st.ab 0, [r5,4]
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brlt r5, r6, 1b
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#ifdef CONFIG_CMDLINE_UBOOT
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; support for bootloader provided cmdline
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; If cmdline passed by u-boot, then
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; r0 = 1 (because ATAGS parsing, now retired, used to use 0)
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; r1 = magic number (board identity)
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; r2 = addr of cmdline string (somewhere in memory/flash)
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brne r0, 1, .Lother_bootup_chores ; u-boot didn't pass cmdline
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breq r2, 0, .Lother_bootup_chores ; or cmdline is NULL
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mov r5, @command_line
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1:
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ldb.ab r6, [r2, 1]
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breq r6, 0, .Lother_bootup_chores
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b.d 1b
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stb.ab r6, [r5, 1]
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#endif
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.Lother_bootup_chores:
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; Identify if running on ISS vs Silicon
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; IDENTITY Reg [ 3 2 1 0 ]
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; (chip-id) ^^^^^ ==> 0xffff for ISS
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lr r0, [identity]
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lsr r3, r0, 16
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cmp r3, 0xffff
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mov.z r4, 0
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mov.nz r4, 1
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st r4, [@running_on_hw]
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; setup "current" tsk and optionally cache it in dedicated r25
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mov r9, @init_task
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SET_CURR_TASK_ON_CPU r9, r0 ; r9 = tsk, r0 = scratch
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; setup stack (fp, sp)
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mov fp, 0
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; tsk->thread_info is really a PAGE, whose bottom hoists stack
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GET_TSK_STACK_BASE r9, sp ; r9 = tsk, sp = stack base(output)
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j start_kernel ; "C" entry point
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#ifdef CONFIG_SMP
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;----------------------------------------------------------------
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; First lines of code run by secondary before jumping to 'C'
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;----------------------------------------------------------------
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.section .init.text, "ax",@progbits
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.type first_lines_of_secondary, @function
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.globl first_lines_of_secondary
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first_lines_of_secondary:
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; setup per-cpu idle task as "current" on this CPU
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ld r0, [@secondary_idle_tsk]
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SET_CURR_TASK_ON_CPU r0, r1
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; setup stack (fp, sp)
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mov fp, 0
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; set it's stack base to tsk->thread_info bottom
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GET_TSK_STACK_BASE r0, sp
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j start_kernel_secondary
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#endif
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