bc8acf2c8c
fresh skbs have ip_summed set to CHECKSUM_NONE (0) We can avoid setting again skb->ip_summed to CHECKSUM_NONE in drivers. Introduce skb_checksum_none_assert() helper so that we keep this assertion documented in driver sources. Change most occurrences of : skb->ip_summed = CHECKSUM_NONE; by : skb_checksum_none_assert(skb); Signed-off-by: Eric Dumazet <eric.dumazet@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
1715 lines
39 KiB
C
1715 lines
39 KiB
C
/*
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* Davicom DM9000 Fast Ethernet driver for Linux.
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* Copyright (C) 1997 Sten Wang
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* (C) Copyright 1997-1998 DAVICOM Semiconductor,Inc. All Rights Reserved.
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*
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* Additional updates, Copyright:
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* Ben Dooks <ben@simtec.co.uk>
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* Sascha Hauer <s.hauer@pengutronix.de>
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*/
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#include <linux/module.h>
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#include <linux/ioport.h>
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#include <linux/netdevice.h>
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#include <linux/etherdevice.h>
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#include <linux/init.h>
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#include <linux/skbuff.h>
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#include <linux/spinlock.h>
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#include <linux/crc32.h>
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#include <linux/mii.h>
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#include <linux/ethtool.h>
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#include <linux/dm9000.h>
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#include <linux/delay.h>
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#include <linux/platform_device.h>
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#include <linux/irq.h>
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#include <linux/slab.h>
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#include <asm/delay.h>
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#include <asm/irq.h>
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#include <asm/io.h>
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#include "dm9000.h"
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/* Board/System/Debug information/definition ---------------- */
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#define DM9000_PHY 0x40 /* PHY address 0x01 */
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#define CARDNAME "dm9000"
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#define DRV_VERSION "1.31"
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/*
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* Transmit timeout, default 5 seconds.
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*/
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static int watchdog = 5000;
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module_param(watchdog, int, 0400);
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MODULE_PARM_DESC(watchdog, "transmit timeout in milliseconds");
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/* DM9000 register address locking.
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*
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* The DM9000 uses an address register to control where data written
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* to the data register goes. This means that the address register
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* must be preserved over interrupts or similar calls.
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*
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* During interrupt and other critical calls, a spinlock is used to
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* protect the system, but the calls themselves save the address
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* in the address register in case they are interrupting another
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* access to the device.
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*
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* For general accesses a lock is provided so that calls which are
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* allowed to sleep are serialised so that the address register does
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* not need to be saved. This lock also serves to serialise access
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* to the EEPROM and PHY access registers which are shared between
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* these two devices.
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*/
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/* The driver supports the original DM9000E, and now the two newer
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* devices, DM9000A and DM9000B.
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*/
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enum dm9000_type {
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TYPE_DM9000E, /* original DM9000 */
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TYPE_DM9000A,
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TYPE_DM9000B
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};
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/* Structure/enum declaration ------------------------------- */
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typedef struct board_info {
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void __iomem *io_addr; /* Register I/O base address */
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void __iomem *io_data; /* Data I/O address */
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u16 irq; /* IRQ */
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u16 tx_pkt_cnt;
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u16 queue_pkt_len;
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u16 queue_start_addr;
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u16 queue_ip_summed;
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u16 dbug_cnt;
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u8 io_mode; /* 0:word, 2:byte */
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u8 phy_addr;
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u8 imr_all;
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unsigned int flags;
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unsigned int in_suspend :1;
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unsigned int wake_supported :1;
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int debug_level;
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enum dm9000_type type;
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void (*inblk)(void __iomem *port, void *data, int length);
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void (*outblk)(void __iomem *port, void *data, int length);
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void (*dumpblk)(void __iomem *port, int length);
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struct device *dev; /* parent device */
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struct resource *addr_res; /* resources found */
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struct resource *data_res;
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struct resource *addr_req; /* resources requested */
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struct resource *data_req;
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struct resource *irq_res;
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int irq_wake;
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struct mutex addr_lock; /* phy and eeprom access lock */
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struct delayed_work phy_poll;
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struct net_device *ndev;
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spinlock_t lock;
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struct mii_if_info mii;
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u32 msg_enable;
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u32 wake_state;
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int rx_csum;
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int can_csum;
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int ip_summed;
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} board_info_t;
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/* debug code */
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#define dm9000_dbg(db, lev, msg...) do { \
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if ((lev) < CONFIG_DM9000_DEBUGLEVEL && \
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(lev) < db->debug_level) { \
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dev_dbg(db->dev, msg); \
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} \
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} while (0)
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static inline board_info_t *to_dm9000_board(struct net_device *dev)
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{
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return netdev_priv(dev);
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}
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/* DM9000 network board routine ---------------------------- */
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static void
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dm9000_reset(board_info_t * db)
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{
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dev_dbg(db->dev, "resetting device\n");
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/* RESET device */
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writeb(DM9000_NCR, db->io_addr);
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udelay(200);
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writeb(NCR_RST, db->io_data);
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udelay(200);
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}
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/*
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* Read a byte from I/O port
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*/
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static u8
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ior(board_info_t * db, int reg)
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{
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writeb(reg, db->io_addr);
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return readb(db->io_data);
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}
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/*
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* Write a byte to I/O port
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*/
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static void
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iow(board_info_t * db, int reg, int value)
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{
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writeb(reg, db->io_addr);
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writeb(value, db->io_data);
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}
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/* routines for sending block to chip */
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static void dm9000_outblk_8bit(void __iomem *reg, void *data, int count)
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{
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writesb(reg, data, count);
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}
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static void dm9000_outblk_16bit(void __iomem *reg, void *data, int count)
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{
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writesw(reg, data, (count+1) >> 1);
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}
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static void dm9000_outblk_32bit(void __iomem *reg, void *data, int count)
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{
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writesl(reg, data, (count+3) >> 2);
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}
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/* input block from chip to memory */
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static void dm9000_inblk_8bit(void __iomem *reg, void *data, int count)
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{
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readsb(reg, data, count);
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}
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static void dm9000_inblk_16bit(void __iomem *reg, void *data, int count)
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{
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readsw(reg, data, (count+1) >> 1);
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}
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static void dm9000_inblk_32bit(void __iomem *reg, void *data, int count)
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{
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readsl(reg, data, (count+3) >> 2);
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}
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/* dump block from chip to null */
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static void dm9000_dumpblk_8bit(void __iomem *reg, int count)
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{
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int i;
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int tmp;
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for (i = 0; i < count; i++)
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tmp = readb(reg);
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}
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static void dm9000_dumpblk_16bit(void __iomem *reg, int count)
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{
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int i;
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int tmp;
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count = (count + 1) >> 1;
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for (i = 0; i < count; i++)
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tmp = readw(reg);
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}
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static void dm9000_dumpblk_32bit(void __iomem *reg, int count)
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{
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int i;
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int tmp;
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count = (count + 3) >> 2;
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for (i = 0; i < count; i++)
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tmp = readl(reg);
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}
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/* dm9000_set_io
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*
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* select the specified set of io routines to use with the
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* device
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*/
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static void dm9000_set_io(struct board_info *db, int byte_width)
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{
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/* use the size of the data resource to work out what IO
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* routines we want to use
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*/
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switch (byte_width) {
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case 1:
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db->dumpblk = dm9000_dumpblk_8bit;
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db->outblk = dm9000_outblk_8bit;
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db->inblk = dm9000_inblk_8bit;
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break;
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case 3:
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dev_dbg(db->dev, ": 3 byte IO, falling back to 16bit\n");
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case 2:
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db->dumpblk = dm9000_dumpblk_16bit;
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db->outblk = dm9000_outblk_16bit;
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db->inblk = dm9000_inblk_16bit;
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break;
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case 4:
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default:
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db->dumpblk = dm9000_dumpblk_32bit;
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db->outblk = dm9000_outblk_32bit;
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db->inblk = dm9000_inblk_32bit;
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break;
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}
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}
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static void dm9000_schedule_poll(board_info_t *db)
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{
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if (db->type == TYPE_DM9000E)
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schedule_delayed_work(&db->phy_poll, HZ * 2);
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}
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static int dm9000_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
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{
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board_info_t *dm = to_dm9000_board(dev);
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if (!netif_running(dev))
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return -EINVAL;
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return generic_mii_ioctl(&dm->mii, if_mii(req), cmd, NULL);
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}
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static unsigned int
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dm9000_read_locked(board_info_t *db, int reg)
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{
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unsigned long flags;
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unsigned int ret;
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spin_lock_irqsave(&db->lock, flags);
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ret = ior(db, reg);
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spin_unlock_irqrestore(&db->lock, flags);
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return ret;
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}
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static int dm9000_wait_eeprom(board_info_t *db)
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{
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unsigned int status;
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int timeout = 8; /* wait max 8msec */
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/* The DM9000 data sheets say we should be able to
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* poll the ERRE bit in EPCR to wait for the EEPROM
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* operation. From testing several chips, this bit
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* does not seem to work.
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*
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* We attempt to use the bit, but fall back to the
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* timeout (which is why we do not return an error
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* on expiry) to say that the EEPROM operation has
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* completed.
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*/
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while (1) {
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status = dm9000_read_locked(db, DM9000_EPCR);
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if ((status & EPCR_ERRE) == 0)
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break;
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msleep(1);
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if (timeout-- < 0) {
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dev_dbg(db->dev, "timeout waiting EEPROM\n");
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break;
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}
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}
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return 0;
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}
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/*
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* Read a word data from EEPROM
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*/
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static void
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dm9000_read_eeprom(board_info_t *db, int offset, u8 *to)
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{
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unsigned long flags;
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if (db->flags & DM9000_PLATF_NO_EEPROM) {
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to[0] = 0xff;
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to[1] = 0xff;
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return;
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}
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mutex_lock(&db->addr_lock);
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spin_lock_irqsave(&db->lock, flags);
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iow(db, DM9000_EPAR, offset);
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iow(db, DM9000_EPCR, EPCR_ERPRR);
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spin_unlock_irqrestore(&db->lock, flags);
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dm9000_wait_eeprom(db);
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/* delay for at-least 150uS */
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msleep(1);
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spin_lock_irqsave(&db->lock, flags);
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iow(db, DM9000_EPCR, 0x0);
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to[0] = ior(db, DM9000_EPDRL);
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to[1] = ior(db, DM9000_EPDRH);
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spin_unlock_irqrestore(&db->lock, flags);
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mutex_unlock(&db->addr_lock);
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}
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/*
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* Write a word data to SROM
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*/
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static void
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dm9000_write_eeprom(board_info_t *db, int offset, u8 *data)
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{
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unsigned long flags;
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if (db->flags & DM9000_PLATF_NO_EEPROM)
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return;
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mutex_lock(&db->addr_lock);
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spin_lock_irqsave(&db->lock, flags);
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iow(db, DM9000_EPAR, offset);
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iow(db, DM9000_EPDRH, data[1]);
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iow(db, DM9000_EPDRL, data[0]);
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iow(db, DM9000_EPCR, EPCR_WEP | EPCR_ERPRW);
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spin_unlock_irqrestore(&db->lock, flags);
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dm9000_wait_eeprom(db);
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mdelay(1); /* wait at least 150uS to clear */
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spin_lock_irqsave(&db->lock, flags);
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iow(db, DM9000_EPCR, 0);
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spin_unlock_irqrestore(&db->lock, flags);
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mutex_unlock(&db->addr_lock);
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}
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|
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/* ethtool ops */
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static void dm9000_get_drvinfo(struct net_device *dev,
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struct ethtool_drvinfo *info)
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{
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board_info_t *dm = to_dm9000_board(dev);
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strcpy(info->driver, CARDNAME);
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strcpy(info->version, DRV_VERSION);
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strcpy(info->bus_info, to_platform_device(dm->dev)->name);
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}
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static u32 dm9000_get_msglevel(struct net_device *dev)
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{
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board_info_t *dm = to_dm9000_board(dev);
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return dm->msg_enable;
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}
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|
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static void dm9000_set_msglevel(struct net_device *dev, u32 value)
|
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{
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board_info_t *dm = to_dm9000_board(dev);
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dm->msg_enable = value;
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}
|
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|
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static int dm9000_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
|
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{
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board_info_t *dm = to_dm9000_board(dev);
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mii_ethtool_gset(&dm->mii, cmd);
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return 0;
|
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}
|
|
|
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static int dm9000_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
|
|
{
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board_info_t *dm = to_dm9000_board(dev);
|
|
|
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return mii_ethtool_sset(&dm->mii, cmd);
|
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}
|
|
|
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static int dm9000_nway_reset(struct net_device *dev)
|
|
{
|
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board_info_t *dm = to_dm9000_board(dev);
|
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return mii_nway_restart(&dm->mii);
|
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}
|
|
|
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static uint32_t dm9000_get_rx_csum(struct net_device *dev)
|
|
{
|
|
board_info_t *dm = to_dm9000_board(dev);
|
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return dm->rx_csum;
|
|
}
|
|
|
|
static int dm9000_set_rx_csum_unlocked(struct net_device *dev, uint32_t data)
|
|
{
|
|
board_info_t *dm = to_dm9000_board(dev);
|
|
|
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if (dm->can_csum) {
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dm->rx_csum = data;
|
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iow(dm, DM9000_RCSR, dm->rx_csum ? RCSR_CSUM : 0);
|
|
|
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return 0;
|
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}
|
|
|
|
return -EOPNOTSUPP;
|
|
}
|
|
|
|
static int dm9000_set_rx_csum(struct net_device *dev, uint32_t data)
|
|
{
|
|
board_info_t *dm = to_dm9000_board(dev);
|
|
unsigned long flags;
|
|
int ret;
|
|
|
|
spin_lock_irqsave(&dm->lock, flags);
|
|
ret = dm9000_set_rx_csum_unlocked(dev, data);
|
|
spin_unlock_irqrestore(&dm->lock, flags);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int dm9000_set_tx_csum(struct net_device *dev, uint32_t data)
|
|
{
|
|
board_info_t *dm = to_dm9000_board(dev);
|
|
int ret = -EOPNOTSUPP;
|
|
|
|
if (dm->can_csum)
|
|
ret = ethtool_op_set_tx_csum(dev, data);
|
|
return ret;
|
|
}
|
|
|
|
static u32 dm9000_get_link(struct net_device *dev)
|
|
{
|
|
board_info_t *dm = to_dm9000_board(dev);
|
|
u32 ret;
|
|
|
|
if (dm->flags & DM9000_PLATF_EXT_PHY)
|
|
ret = mii_link_ok(&dm->mii);
|
|
else
|
|
ret = dm9000_read_locked(dm, DM9000_NSR) & NSR_LINKST ? 1 : 0;
|
|
|
|
return ret;
|
|
}
|
|
|
|
#define DM_EEPROM_MAGIC (0x444D394B)
|
|
|
|
static int dm9000_get_eeprom_len(struct net_device *dev)
|
|
{
|
|
return 128;
|
|
}
|
|
|
|
static int dm9000_get_eeprom(struct net_device *dev,
|
|
struct ethtool_eeprom *ee, u8 *data)
|
|
{
|
|
board_info_t *dm = to_dm9000_board(dev);
|
|
int offset = ee->offset;
|
|
int len = ee->len;
|
|
int i;
|
|
|
|
/* EEPROM access is aligned to two bytes */
|
|
|
|
if ((len & 1) != 0 || (offset & 1) != 0)
|
|
return -EINVAL;
|
|
|
|
if (dm->flags & DM9000_PLATF_NO_EEPROM)
|
|
return -ENOENT;
|
|
|
|
ee->magic = DM_EEPROM_MAGIC;
|
|
|
|
for (i = 0; i < len; i += 2)
|
|
dm9000_read_eeprom(dm, (offset + i) / 2, data + i);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int dm9000_set_eeprom(struct net_device *dev,
|
|
struct ethtool_eeprom *ee, u8 *data)
|
|
{
|
|
board_info_t *dm = to_dm9000_board(dev);
|
|
int offset = ee->offset;
|
|
int len = ee->len;
|
|
int i;
|
|
|
|
/* EEPROM access is aligned to two bytes */
|
|
|
|
if ((len & 1) != 0 || (offset & 1) != 0)
|
|
return -EINVAL;
|
|
|
|
if (dm->flags & DM9000_PLATF_NO_EEPROM)
|
|
return -ENOENT;
|
|
|
|
if (ee->magic != DM_EEPROM_MAGIC)
|
|
return -EINVAL;
|
|
|
|
for (i = 0; i < len; i += 2)
|
|
dm9000_write_eeprom(dm, (offset + i) / 2, data + i);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void dm9000_get_wol(struct net_device *dev, struct ethtool_wolinfo *w)
|
|
{
|
|
board_info_t *dm = to_dm9000_board(dev);
|
|
|
|
memset(w, 0, sizeof(struct ethtool_wolinfo));
|
|
|
|
/* note, we could probably support wake-phy too */
|
|
w->supported = dm->wake_supported ? WAKE_MAGIC : 0;
|
|
w->wolopts = dm->wake_state;
|
|
}
|
|
|
|
static int dm9000_set_wol(struct net_device *dev, struct ethtool_wolinfo *w)
|
|
{
|
|
board_info_t *dm = to_dm9000_board(dev);
|
|
unsigned long flags;
|
|
u32 opts = w->wolopts;
|
|
u32 wcr = 0;
|
|
|
|
if (!dm->wake_supported)
|
|
return -EOPNOTSUPP;
|
|
|
|
if (opts & ~WAKE_MAGIC)
|
|
return -EINVAL;
|
|
|
|
if (opts & WAKE_MAGIC)
|
|
wcr |= WCR_MAGICEN;
|
|
|
|
mutex_lock(&dm->addr_lock);
|
|
|
|
spin_lock_irqsave(&dm->lock, flags);
|
|
iow(dm, DM9000_WCR, wcr);
|
|
spin_unlock_irqrestore(&dm->lock, flags);
|
|
|
|
mutex_unlock(&dm->addr_lock);
|
|
|
|
if (dm->wake_state != opts) {
|
|
/* change in wol state, update IRQ state */
|
|
|
|
if (!dm->wake_state)
|
|
set_irq_wake(dm->irq_wake, 1);
|
|
else if (dm->wake_state & !opts)
|
|
set_irq_wake(dm->irq_wake, 0);
|
|
}
|
|
|
|
dm->wake_state = opts;
|
|
return 0;
|
|
}
|
|
|
|
static const struct ethtool_ops dm9000_ethtool_ops = {
|
|
.get_drvinfo = dm9000_get_drvinfo,
|
|
.get_settings = dm9000_get_settings,
|
|
.set_settings = dm9000_set_settings,
|
|
.get_msglevel = dm9000_get_msglevel,
|
|
.set_msglevel = dm9000_set_msglevel,
|
|
.nway_reset = dm9000_nway_reset,
|
|
.get_link = dm9000_get_link,
|
|
.get_wol = dm9000_get_wol,
|
|
.set_wol = dm9000_set_wol,
|
|
.get_eeprom_len = dm9000_get_eeprom_len,
|
|
.get_eeprom = dm9000_get_eeprom,
|
|
.set_eeprom = dm9000_set_eeprom,
|
|
.get_rx_csum = dm9000_get_rx_csum,
|
|
.set_rx_csum = dm9000_set_rx_csum,
|
|
.get_tx_csum = ethtool_op_get_tx_csum,
|
|
.set_tx_csum = dm9000_set_tx_csum,
|
|
};
|
|
|
|
static void dm9000_show_carrier(board_info_t *db,
|
|
unsigned carrier, unsigned nsr)
|
|
{
|
|
struct net_device *ndev = db->ndev;
|
|
unsigned ncr = dm9000_read_locked(db, DM9000_NCR);
|
|
|
|
if (carrier)
|
|
dev_info(db->dev, "%s: link up, %dMbps, %s-duplex, no LPA\n",
|
|
ndev->name, (nsr & NSR_SPEED) ? 10 : 100,
|
|
(ncr & NCR_FDX) ? "full" : "half");
|
|
else
|
|
dev_info(db->dev, "%s: link down\n", ndev->name);
|
|
}
|
|
|
|
static void
|
|
dm9000_poll_work(struct work_struct *w)
|
|
{
|
|
struct delayed_work *dw = to_delayed_work(w);
|
|
board_info_t *db = container_of(dw, board_info_t, phy_poll);
|
|
struct net_device *ndev = db->ndev;
|
|
|
|
if (db->flags & DM9000_PLATF_SIMPLE_PHY &&
|
|
!(db->flags & DM9000_PLATF_EXT_PHY)) {
|
|
unsigned nsr = dm9000_read_locked(db, DM9000_NSR);
|
|
unsigned old_carrier = netif_carrier_ok(ndev) ? 1 : 0;
|
|
unsigned new_carrier;
|
|
|
|
new_carrier = (nsr & NSR_LINKST) ? 1 : 0;
|
|
|
|
if (old_carrier != new_carrier) {
|
|
if (netif_msg_link(db))
|
|
dm9000_show_carrier(db, new_carrier, nsr);
|
|
|
|
if (!new_carrier)
|
|
netif_carrier_off(ndev);
|
|
else
|
|
netif_carrier_on(ndev);
|
|
}
|
|
} else
|
|
mii_check_media(&db->mii, netif_msg_link(db), 0);
|
|
|
|
if (netif_running(ndev))
|
|
dm9000_schedule_poll(db);
|
|
}
|
|
|
|
/* dm9000_release_board
|
|
*
|
|
* release a board, and any mapped resources
|
|
*/
|
|
|
|
static void
|
|
dm9000_release_board(struct platform_device *pdev, struct board_info *db)
|
|
{
|
|
/* unmap our resources */
|
|
|
|
iounmap(db->io_addr);
|
|
iounmap(db->io_data);
|
|
|
|
/* release the resources */
|
|
|
|
release_resource(db->data_req);
|
|
kfree(db->data_req);
|
|
|
|
release_resource(db->addr_req);
|
|
kfree(db->addr_req);
|
|
}
|
|
|
|
static unsigned char dm9000_type_to_char(enum dm9000_type type)
|
|
{
|
|
switch (type) {
|
|
case TYPE_DM9000E: return 'e';
|
|
case TYPE_DM9000A: return 'a';
|
|
case TYPE_DM9000B: return 'b';
|
|
}
|
|
|
|
return '?';
|
|
}
|
|
|
|
/*
|
|
* Set DM9000 multicast address
|
|
*/
|
|
static void
|
|
dm9000_hash_table_unlocked(struct net_device *dev)
|
|
{
|
|
board_info_t *db = netdev_priv(dev);
|
|
struct netdev_hw_addr *ha;
|
|
int i, oft;
|
|
u32 hash_val;
|
|
u16 hash_table[4];
|
|
u8 rcr = RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN;
|
|
|
|
dm9000_dbg(db, 1, "entering %s\n", __func__);
|
|
|
|
for (i = 0, oft = DM9000_PAR; i < 6; i++, oft++)
|
|
iow(db, oft, dev->dev_addr[i]);
|
|
|
|
/* Clear Hash Table */
|
|
for (i = 0; i < 4; i++)
|
|
hash_table[i] = 0x0;
|
|
|
|
/* broadcast address */
|
|
hash_table[3] = 0x8000;
|
|
|
|
if (dev->flags & IFF_PROMISC)
|
|
rcr |= RCR_PRMSC;
|
|
|
|
if (dev->flags & IFF_ALLMULTI)
|
|
rcr |= RCR_ALL;
|
|
|
|
/* the multicast address in Hash Table : 64 bits */
|
|
netdev_for_each_mc_addr(ha, dev) {
|
|
hash_val = ether_crc_le(6, ha->addr) & 0x3f;
|
|
hash_table[hash_val / 16] |= (u16) 1 << (hash_val % 16);
|
|
}
|
|
|
|
/* Write the hash table to MAC MD table */
|
|
for (i = 0, oft = DM9000_MAR; i < 4; i++) {
|
|
iow(db, oft++, hash_table[i]);
|
|
iow(db, oft++, hash_table[i] >> 8);
|
|
}
|
|
|
|
iow(db, DM9000_RCR, rcr);
|
|
}
|
|
|
|
static void
|
|
dm9000_hash_table(struct net_device *dev)
|
|
{
|
|
board_info_t *db = netdev_priv(dev);
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&db->lock, flags);
|
|
dm9000_hash_table_unlocked(dev);
|
|
spin_unlock_irqrestore(&db->lock, flags);
|
|
}
|
|
|
|
/*
|
|
* Initialize dm9000 board
|
|
*/
|
|
static void
|
|
dm9000_init_dm9000(struct net_device *dev)
|
|
{
|
|
board_info_t *db = netdev_priv(dev);
|
|
unsigned int imr;
|
|
unsigned int ncr;
|
|
|
|
dm9000_dbg(db, 1, "entering %s\n", __func__);
|
|
|
|
/* I/O mode */
|
|
db->io_mode = ior(db, DM9000_ISR) >> 6; /* ISR bit7:6 keeps I/O mode */
|
|
|
|
/* Checksum mode */
|
|
dm9000_set_rx_csum_unlocked(dev, db->rx_csum);
|
|
|
|
/* GPIO0 on pre-activate PHY */
|
|
iow(db, DM9000_GPR, 0); /* REG_1F bit0 activate phyxcer */
|
|
iow(db, DM9000_GPCR, GPCR_GEP_CNTL); /* Let GPIO0 output */
|
|
iow(db, DM9000_GPR, 0); /* Enable PHY */
|
|
|
|
ncr = (db->flags & DM9000_PLATF_EXT_PHY) ? NCR_EXT_PHY : 0;
|
|
|
|
/* if wol is needed, then always set NCR_WAKEEN otherwise we end
|
|
* up dumping the wake events if we disable this. There is already
|
|
* a wake-mask in DM9000_WCR */
|
|
if (db->wake_supported)
|
|
ncr |= NCR_WAKEEN;
|
|
|
|
iow(db, DM9000_NCR, ncr);
|
|
|
|
/* Program operating register */
|
|
iow(db, DM9000_TCR, 0); /* TX Polling clear */
|
|
iow(db, DM9000_BPTR, 0x3f); /* Less 3Kb, 200us */
|
|
iow(db, DM9000_FCR, 0xff); /* Flow Control */
|
|
iow(db, DM9000_SMCR, 0); /* Special Mode */
|
|
/* clear TX status */
|
|
iow(db, DM9000_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END);
|
|
iow(db, DM9000_ISR, ISR_CLR_STATUS); /* Clear interrupt status */
|
|
|
|
/* Set address filter table */
|
|
dm9000_hash_table_unlocked(dev);
|
|
|
|
imr = IMR_PAR | IMR_PTM | IMR_PRM;
|
|
if (db->type != TYPE_DM9000E)
|
|
imr |= IMR_LNKCHNG;
|
|
|
|
db->imr_all = imr;
|
|
|
|
/* Enable TX/RX interrupt mask */
|
|
iow(db, DM9000_IMR, imr);
|
|
|
|
/* Init Driver variable */
|
|
db->tx_pkt_cnt = 0;
|
|
db->queue_pkt_len = 0;
|
|
dev->trans_start = jiffies;
|
|
}
|
|
|
|
/* Our watchdog timed out. Called by the networking layer */
|
|
static void dm9000_timeout(struct net_device *dev)
|
|
{
|
|
board_info_t *db = netdev_priv(dev);
|
|
u8 reg_save;
|
|
unsigned long flags;
|
|
|
|
/* Save previous register address */
|
|
reg_save = readb(db->io_addr);
|
|
spin_lock_irqsave(&db->lock, flags);
|
|
|
|
netif_stop_queue(dev);
|
|
dm9000_reset(db);
|
|
dm9000_init_dm9000(dev);
|
|
/* We can accept TX packets again */
|
|
dev->trans_start = jiffies; /* prevent tx timeout */
|
|
netif_wake_queue(dev);
|
|
|
|
/* Restore previous register address */
|
|
writeb(reg_save, db->io_addr);
|
|
spin_unlock_irqrestore(&db->lock, flags);
|
|
}
|
|
|
|
static void dm9000_send_packet(struct net_device *dev,
|
|
int ip_summed,
|
|
u16 pkt_len)
|
|
{
|
|
board_info_t *dm = to_dm9000_board(dev);
|
|
|
|
/* The DM9000 is not smart enough to leave fragmented packets alone. */
|
|
if (dm->ip_summed != ip_summed) {
|
|
if (ip_summed == CHECKSUM_NONE)
|
|
iow(dm, DM9000_TCCR, 0);
|
|
else
|
|
iow(dm, DM9000_TCCR, TCCR_IP | TCCR_UDP | TCCR_TCP);
|
|
dm->ip_summed = ip_summed;
|
|
}
|
|
|
|
/* Set TX length to DM9000 */
|
|
iow(dm, DM9000_TXPLL, pkt_len);
|
|
iow(dm, DM9000_TXPLH, pkt_len >> 8);
|
|
|
|
/* Issue TX polling command */
|
|
iow(dm, DM9000_TCR, TCR_TXREQ); /* Cleared after TX complete */
|
|
}
|
|
|
|
/*
|
|
* Hardware start transmission.
|
|
* Send a packet to media from the upper layer.
|
|
*/
|
|
static int
|
|
dm9000_start_xmit(struct sk_buff *skb, struct net_device *dev)
|
|
{
|
|
unsigned long flags;
|
|
board_info_t *db = netdev_priv(dev);
|
|
|
|
dm9000_dbg(db, 3, "%s:\n", __func__);
|
|
|
|
if (db->tx_pkt_cnt > 1)
|
|
return NETDEV_TX_BUSY;
|
|
|
|
spin_lock_irqsave(&db->lock, flags);
|
|
|
|
/* Move data to DM9000 TX RAM */
|
|
writeb(DM9000_MWCMD, db->io_addr);
|
|
|
|
(db->outblk)(db->io_data, skb->data, skb->len);
|
|
dev->stats.tx_bytes += skb->len;
|
|
|
|
db->tx_pkt_cnt++;
|
|
/* TX control: First packet immediately send, second packet queue */
|
|
if (db->tx_pkt_cnt == 1) {
|
|
dm9000_send_packet(dev, skb->ip_summed, skb->len);
|
|
} else {
|
|
/* Second packet */
|
|
db->queue_pkt_len = skb->len;
|
|
db->queue_ip_summed = skb->ip_summed;
|
|
netif_stop_queue(dev);
|
|
}
|
|
|
|
spin_unlock_irqrestore(&db->lock, flags);
|
|
|
|
/* free this SKB */
|
|
dev_kfree_skb(skb);
|
|
|
|
return NETDEV_TX_OK;
|
|
}
|
|
|
|
/*
|
|
* DM9000 interrupt handler
|
|
* receive the packet to upper layer, free the transmitted packet
|
|
*/
|
|
|
|
static void dm9000_tx_done(struct net_device *dev, board_info_t *db)
|
|
{
|
|
int tx_status = ior(db, DM9000_NSR); /* Got TX status */
|
|
|
|
if (tx_status & (NSR_TX2END | NSR_TX1END)) {
|
|
/* One packet sent complete */
|
|
db->tx_pkt_cnt--;
|
|
dev->stats.tx_packets++;
|
|
|
|
if (netif_msg_tx_done(db))
|
|
dev_dbg(db->dev, "tx done, NSR %02x\n", tx_status);
|
|
|
|
/* Queue packet check & send */
|
|
if (db->tx_pkt_cnt > 0)
|
|
dm9000_send_packet(dev, db->queue_ip_summed,
|
|
db->queue_pkt_len);
|
|
netif_wake_queue(dev);
|
|
}
|
|
}
|
|
|
|
struct dm9000_rxhdr {
|
|
u8 RxPktReady;
|
|
u8 RxStatus;
|
|
__le16 RxLen;
|
|
} __packed;
|
|
|
|
/*
|
|
* Received a packet and pass to upper layer
|
|
*/
|
|
static void
|
|
dm9000_rx(struct net_device *dev)
|
|
{
|
|
board_info_t *db = netdev_priv(dev);
|
|
struct dm9000_rxhdr rxhdr;
|
|
struct sk_buff *skb;
|
|
u8 rxbyte, *rdptr;
|
|
bool GoodPacket;
|
|
int RxLen;
|
|
|
|
/* Check packet ready or not */
|
|
do {
|
|
ior(db, DM9000_MRCMDX); /* Dummy read */
|
|
|
|
/* Get most updated data */
|
|
rxbyte = readb(db->io_data);
|
|
|
|
/* Status check: this byte must be 0 or 1 */
|
|
if (rxbyte & DM9000_PKT_ERR) {
|
|
dev_warn(db->dev, "status check fail: %d\n", rxbyte);
|
|
iow(db, DM9000_RCR, 0x00); /* Stop Device */
|
|
iow(db, DM9000_ISR, IMR_PAR); /* Stop INT request */
|
|
return;
|
|
}
|
|
|
|
if (!(rxbyte & DM9000_PKT_RDY))
|
|
return;
|
|
|
|
/* A packet ready now & Get status/length */
|
|
GoodPacket = true;
|
|
writeb(DM9000_MRCMD, db->io_addr);
|
|
|
|
(db->inblk)(db->io_data, &rxhdr, sizeof(rxhdr));
|
|
|
|
RxLen = le16_to_cpu(rxhdr.RxLen);
|
|
|
|
if (netif_msg_rx_status(db))
|
|
dev_dbg(db->dev, "RX: status %02x, length %04x\n",
|
|
rxhdr.RxStatus, RxLen);
|
|
|
|
/* Packet Status check */
|
|
if (RxLen < 0x40) {
|
|
GoodPacket = false;
|
|
if (netif_msg_rx_err(db))
|
|
dev_dbg(db->dev, "RX: Bad Packet (runt)\n");
|
|
}
|
|
|
|
if (RxLen > DM9000_PKT_MAX) {
|
|
dev_dbg(db->dev, "RST: RX Len:%x\n", RxLen);
|
|
}
|
|
|
|
/* rxhdr.RxStatus is identical to RSR register. */
|
|
if (rxhdr.RxStatus & (RSR_FOE | RSR_CE | RSR_AE |
|
|
RSR_PLE | RSR_RWTO |
|
|
RSR_LCS | RSR_RF)) {
|
|
GoodPacket = false;
|
|
if (rxhdr.RxStatus & RSR_FOE) {
|
|
if (netif_msg_rx_err(db))
|
|
dev_dbg(db->dev, "fifo error\n");
|
|
dev->stats.rx_fifo_errors++;
|
|
}
|
|
if (rxhdr.RxStatus & RSR_CE) {
|
|
if (netif_msg_rx_err(db))
|
|
dev_dbg(db->dev, "crc error\n");
|
|
dev->stats.rx_crc_errors++;
|
|
}
|
|
if (rxhdr.RxStatus & RSR_RF) {
|
|
if (netif_msg_rx_err(db))
|
|
dev_dbg(db->dev, "length error\n");
|
|
dev->stats.rx_length_errors++;
|
|
}
|
|
}
|
|
|
|
/* Move data from DM9000 */
|
|
if (GoodPacket &&
|
|
((skb = dev_alloc_skb(RxLen + 4)) != NULL)) {
|
|
skb_reserve(skb, 2);
|
|
rdptr = (u8 *) skb_put(skb, RxLen - 4);
|
|
|
|
/* Read received packet from RX SRAM */
|
|
|
|
(db->inblk)(db->io_data, rdptr, RxLen);
|
|
dev->stats.rx_bytes += RxLen;
|
|
|
|
/* Pass to upper layer */
|
|
skb->protocol = eth_type_trans(skb, dev);
|
|
if (db->rx_csum) {
|
|
if ((((rxbyte & 0x1c) << 3) & rxbyte) == 0)
|
|
skb->ip_summed = CHECKSUM_UNNECESSARY;
|
|
else
|
|
skb_checksum_none_assert(skb);
|
|
}
|
|
netif_rx(skb);
|
|
dev->stats.rx_packets++;
|
|
|
|
} else {
|
|
/* need to dump the packet's data */
|
|
|
|
(db->dumpblk)(db->io_data, RxLen);
|
|
}
|
|
} while (rxbyte & DM9000_PKT_RDY);
|
|
}
|
|
|
|
static irqreturn_t dm9000_interrupt(int irq, void *dev_id)
|
|
{
|
|
struct net_device *dev = dev_id;
|
|
board_info_t *db = netdev_priv(dev);
|
|
int int_status;
|
|
unsigned long flags;
|
|
u8 reg_save;
|
|
|
|
dm9000_dbg(db, 3, "entering %s\n", __func__);
|
|
|
|
/* A real interrupt coming */
|
|
|
|
/* holders of db->lock must always block IRQs */
|
|
spin_lock_irqsave(&db->lock, flags);
|
|
|
|
/* Save previous register address */
|
|
reg_save = readb(db->io_addr);
|
|
|
|
/* Disable all interrupts */
|
|
iow(db, DM9000_IMR, IMR_PAR);
|
|
|
|
/* Got DM9000 interrupt status */
|
|
int_status = ior(db, DM9000_ISR); /* Got ISR */
|
|
iow(db, DM9000_ISR, int_status); /* Clear ISR status */
|
|
|
|
if (netif_msg_intr(db))
|
|
dev_dbg(db->dev, "interrupt status %02x\n", int_status);
|
|
|
|
/* Received the coming packet */
|
|
if (int_status & ISR_PRS)
|
|
dm9000_rx(dev);
|
|
|
|
/* Trnasmit Interrupt check */
|
|
if (int_status & ISR_PTS)
|
|
dm9000_tx_done(dev, db);
|
|
|
|
if (db->type != TYPE_DM9000E) {
|
|
if (int_status & ISR_LNKCHNG) {
|
|
/* fire a link-change request */
|
|
schedule_delayed_work(&db->phy_poll, 1);
|
|
}
|
|
}
|
|
|
|
/* Re-enable interrupt mask */
|
|
iow(db, DM9000_IMR, db->imr_all);
|
|
|
|
/* Restore previous register address */
|
|
writeb(reg_save, db->io_addr);
|
|
|
|
spin_unlock_irqrestore(&db->lock, flags);
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static irqreturn_t dm9000_wol_interrupt(int irq, void *dev_id)
|
|
{
|
|
struct net_device *dev = dev_id;
|
|
board_info_t *db = netdev_priv(dev);
|
|
unsigned long flags;
|
|
unsigned nsr, wcr;
|
|
|
|
spin_lock_irqsave(&db->lock, flags);
|
|
|
|
nsr = ior(db, DM9000_NSR);
|
|
wcr = ior(db, DM9000_WCR);
|
|
|
|
dev_dbg(db->dev, "%s: NSR=0x%02x, WCR=0x%02x\n", __func__, nsr, wcr);
|
|
|
|
if (nsr & NSR_WAKEST) {
|
|
/* clear, so we can avoid */
|
|
iow(db, DM9000_NSR, NSR_WAKEST);
|
|
|
|
if (wcr & WCR_LINKST)
|
|
dev_info(db->dev, "wake by link status change\n");
|
|
if (wcr & WCR_SAMPLEST)
|
|
dev_info(db->dev, "wake by sample packet\n");
|
|
if (wcr & WCR_MAGICST )
|
|
dev_info(db->dev, "wake by magic packet\n");
|
|
if (!(wcr & (WCR_LINKST | WCR_SAMPLEST | WCR_MAGICST)))
|
|
dev_err(db->dev, "wake signalled with no reason? "
|
|
"NSR=0x%02x, WSR=0x%02x\n", nsr, wcr);
|
|
|
|
}
|
|
|
|
spin_unlock_irqrestore(&db->lock, flags);
|
|
|
|
return (nsr & NSR_WAKEST) ? IRQ_HANDLED : IRQ_NONE;
|
|
}
|
|
|
|
#ifdef CONFIG_NET_POLL_CONTROLLER
|
|
/*
|
|
*Used by netconsole
|
|
*/
|
|
static void dm9000_poll_controller(struct net_device *dev)
|
|
{
|
|
disable_irq(dev->irq);
|
|
dm9000_interrupt(dev->irq, dev);
|
|
enable_irq(dev->irq);
|
|
}
|
|
#endif
|
|
|
|
/*
|
|
* Open the interface.
|
|
* The interface is opened whenever "ifconfig" actives it.
|
|
*/
|
|
static int
|
|
dm9000_open(struct net_device *dev)
|
|
{
|
|
board_info_t *db = netdev_priv(dev);
|
|
unsigned long irqflags = db->irq_res->flags & IRQF_TRIGGER_MASK;
|
|
|
|
if (netif_msg_ifup(db))
|
|
dev_dbg(db->dev, "enabling %s\n", dev->name);
|
|
|
|
/* If there is no IRQ type specified, default to something that
|
|
* may work, and tell the user that this is a problem */
|
|
|
|
if (irqflags == IRQF_TRIGGER_NONE)
|
|
dev_warn(db->dev, "WARNING: no IRQ resource flags set.\n");
|
|
|
|
irqflags |= IRQF_SHARED;
|
|
|
|
if (request_irq(dev->irq, dm9000_interrupt, irqflags, dev->name, dev))
|
|
return -EAGAIN;
|
|
|
|
/* Initialize DM9000 board */
|
|
dm9000_reset(db);
|
|
dm9000_init_dm9000(dev);
|
|
|
|
/* Init driver variable */
|
|
db->dbug_cnt = 0;
|
|
|
|
mii_check_media(&db->mii, netif_msg_link(db), 1);
|
|
netif_start_queue(dev);
|
|
|
|
dm9000_schedule_poll(db);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Sleep, either by using msleep() or if we are suspending, then
|
|
* use mdelay() to sleep.
|
|
*/
|
|
static void dm9000_msleep(board_info_t *db, unsigned int ms)
|
|
{
|
|
if (db->in_suspend)
|
|
mdelay(ms);
|
|
else
|
|
msleep(ms);
|
|
}
|
|
|
|
/*
|
|
* Read a word from phyxcer
|
|
*/
|
|
static int
|
|
dm9000_phy_read(struct net_device *dev, int phy_reg_unused, int reg)
|
|
{
|
|
board_info_t *db = netdev_priv(dev);
|
|
unsigned long flags;
|
|
unsigned int reg_save;
|
|
int ret;
|
|
|
|
mutex_lock(&db->addr_lock);
|
|
|
|
spin_lock_irqsave(&db->lock,flags);
|
|
|
|
/* Save previous register address */
|
|
reg_save = readb(db->io_addr);
|
|
|
|
/* Fill the phyxcer register into REG_0C */
|
|
iow(db, DM9000_EPAR, DM9000_PHY | reg);
|
|
|
|
iow(db, DM9000_EPCR, EPCR_ERPRR | EPCR_EPOS); /* Issue phyxcer read command */
|
|
|
|
writeb(reg_save, db->io_addr);
|
|
spin_unlock_irqrestore(&db->lock,flags);
|
|
|
|
dm9000_msleep(db, 1); /* Wait read complete */
|
|
|
|
spin_lock_irqsave(&db->lock,flags);
|
|
reg_save = readb(db->io_addr);
|
|
|
|
iow(db, DM9000_EPCR, 0x0); /* Clear phyxcer read command */
|
|
|
|
/* The read data keeps on REG_0D & REG_0E */
|
|
ret = (ior(db, DM9000_EPDRH) << 8) | ior(db, DM9000_EPDRL);
|
|
|
|
/* restore the previous address */
|
|
writeb(reg_save, db->io_addr);
|
|
spin_unlock_irqrestore(&db->lock,flags);
|
|
|
|
mutex_unlock(&db->addr_lock);
|
|
|
|
dm9000_dbg(db, 5, "phy_read[%02x] -> %04x\n", reg, ret);
|
|
return ret;
|
|
}
|
|
|
|
/*
|
|
* Write a word to phyxcer
|
|
*/
|
|
static void
|
|
dm9000_phy_write(struct net_device *dev,
|
|
int phyaddr_unused, int reg, int value)
|
|
{
|
|
board_info_t *db = netdev_priv(dev);
|
|
unsigned long flags;
|
|
unsigned long reg_save;
|
|
|
|
dm9000_dbg(db, 5, "phy_write[%02x] = %04x\n", reg, value);
|
|
mutex_lock(&db->addr_lock);
|
|
|
|
spin_lock_irqsave(&db->lock,flags);
|
|
|
|
/* Save previous register address */
|
|
reg_save = readb(db->io_addr);
|
|
|
|
/* Fill the phyxcer register into REG_0C */
|
|
iow(db, DM9000_EPAR, DM9000_PHY | reg);
|
|
|
|
/* Fill the written data into REG_0D & REG_0E */
|
|
iow(db, DM9000_EPDRL, value);
|
|
iow(db, DM9000_EPDRH, value >> 8);
|
|
|
|
iow(db, DM9000_EPCR, EPCR_EPOS | EPCR_ERPRW); /* Issue phyxcer write command */
|
|
|
|
writeb(reg_save, db->io_addr);
|
|
spin_unlock_irqrestore(&db->lock, flags);
|
|
|
|
dm9000_msleep(db, 1); /* Wait write complete */
|
|
|
|
spin_lock_irqsave(&db->lock,flags);
|
|
reg_save = readb(db->io_addr);
|
|
|
|
iow(db, DM9000_EPCR, 0x0); /* Clear phyxcer write command */
|
|
|
|
/* restore the previous address */
|
|
writeb(reg_save, db->io_addr);
|
|
|
|
spin_unlock_irqrestore(&db->lock, flags);
|
|
mutex_unlock(&db->addr_lock);
|
|
}
|
|
|
|
static void
|
|
dm9000_shutdown(struct net_device *dev)
|
|
{
|
|
board_info_t *db = netdev_priv(dev);
|
|
|
|
/* RESET device */
|
|
dm9000_phy_write(dev, 0, MII_BMCR, BMCR_RESET); /* PHY RESET */
|
|
iow(db, DM9000_GPR, 0x01); /* Power-Down PHY */
|
|
iow(db, DM9000_IMR, IMR_PAR); /* Disable all interrupt */
|
|
iow(db, DM9000_RCR, 0x00); /* Disable RX */
|
|
}
|
|
|
|
/*
|
|
* Stop the interface.
|
|
* The interface is stopped when it is brought.
|
|
*/
|
|
static int
|
|
dm9000_stop(struct net_device *ndev)
|
|
{
|
|
board_info_t *db = netdev_priv(ndev);
|
|
|
|
if (netif_msg_ifdown(db))
|
|
dev_dbg(db->dev, "shutting down %s\n", ndev->name);
|
|
|
|
cancel_delayed_work_sync(&db->phy_poll);
|
|
|
|
netif_stop_queue(ndev);
|
|
netif_carrier_off(ndev);
|
|
|
|
/* free interrupt */
|
|
free_irq(ndev->irq, ndev);
|
|
|
|
dm9000_shutdown(ndev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct net_device_ops dm9000_netdev_ops = {
|
|
.ndo_open = dm9000_open,
|
|
.ndo_stop = dm9000_stop,
|
|
.ndo_start_xmit = dm9000_start_xmit,
|
|
.ndo_tx_timeout = dm9000_timeout,
|
|
.ndo_set_multicast_list = dm9000_hash_table,
|
|
.ndo_do_ioctl = dm9000_ioctl,
|
|
.ndo_change_mtu = eth_change_mtu,
|
|
.ndo_validate_addr = eth_validate_addr,
|
|
.ndo_set_mac_address = eth_mac_addr,
|
|
#ifdef CONFIG_NET_POLL_CONTROLLER
|
|
.ndo_poll_controller = dm9000_poll_controller,
|
|
#endif
|
|
};
|
|
|
|
/*
|
|
* Search DM9000 board, allocate space and register it
|
|
*/
|
|
static int __devinit
|
|
dm9000_probe(struct platform_device *pdev)
|
|
{
|
|
struct dm9000_plat_data *pdata = pdev->dev.platform_data;
|
|
struct board_info *db; /* Point a board information structure */
|
|
struct net_device *ndev;
|
|
const unsigned char *mac_src;
|
|
int ret = 0;
|
|
int iosize;
|
|
int i;
|
|
u32 id_val;
|
|
|
|
/* Init network device */
|
|
ndev = alloc_etherdev(sizeof(struct board_info));
|
|
if (!ndev) {
|
|
dev_err(&pdev->dev, "could not allocate device.\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
SET_NETDEV_DEV(ndev, &pdev->dev);
|
|
|
|
dev_dbg(&pdev->dev, "dm9000_probe()\n");
|
|
|
|
/* setup board info structure */
|
|
db = netdev_priv(ndev);
|
|
|
|
db->dev = &pdev->dev;
|
|
db->ndev = ndev;
|
|
|
|
spin_lock_init(&db->lock);
|
|
mutex_init(&db->addr_lock);
|
|
|
|
INIT_DELAYED_WORK(&db->phy_poll, dm9000_poll_work);
|
|
|
|
db->addr_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
db->data_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
|
|
db->irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
|
|
|
|
if (db->addr_res == NULL || db->data_res == NULL ||
|
|
db->irq_res == NULL) {
|
|
dev_err(db->dev, "insufficient resources\n");
|
|
ret = -ENOENT;
|
|
goto out;
|
|
}
|
|
|
|
db->irq_wake = platform_get_irq(pdev, 1);
|
|
if (db->irq_wake >= 0) {
|
|
dev_dbg(db->dev, "wakeup irq %d\n", db->irq_wake);
|
|
|
|
ret = request_irq(db->irq_wake, dm9000_wol_interrupt,
|
|
IRQF_SHARED, dev_name(db->dev), ndev);
|
|
if (ret) {
|
|
dev_err(db->dev, "cannot get wakeup irq (%d)\n", ret);
|
|
} else {
|
|
|
|
/* test to see if irq is really wakeup capable */
|
|
ret = set_irq_wake(db->irq_wake, 1);
|
|
if (ret) {
|
|
dev_err(db->dev, "irq %d cannot set wakeup (%d)\n",
|
|
db->irq_wake, ret);
|
|
ret = 0;
|
|
} else {
|
|
set_irq_wake(db->irq_wake, 0);
|
|
db->wake_supported = 1;
|
|
}
|
|
}
|
|
}
|
|
|
|
iosize = resource_size(db->addr_res);
|
|
db->addr_req = request_mem_region(db->addr_res->start, iosize,
|
|
pdev->name);
|
|
|
|
if (db->addr_req == NULL) {
|
|
dev_err(db->dev, "cannot claim address reg area\n");
|
|
ret = -EIO;
|
|
goto out;
|
|
}
|
|
|
|
db->io_addr = ioremap(db->addr_res->start, iosize);
|
|
|
|
if (db->io_addr == NULL) {
|
|
dev_err(db->dev, "failed to ioremap address reg\n");
|
|
ret = -EINVAL;
|
|
goto out;
|
|
}
|
|
|
|
iosize = resource_size(db->data_res);
|
|
db->data_req = request_mem_region(db->data_res->start, iosize,
|
|
pdev->name);
|
|
|
|
if (db->data_req == NULL) {
|
|
dev_err(db->dev, "cannot claim data reg area\n");
|
|
ret = -EIO;
|
|
goto out;
|
|
}
|
|
|
|
db->io_data = ioremap(db->data_res->start, iosize);
|
|
|
|
if (db->io_data == NULL) {
|
|
dev_err(db->dev, "failed to ioremap data reg\n");
|
|
ret = -EINVAL;
|
|
goto out;
|
|
}
|
|
|
|
/* fill in parameters for net-dev structure */
|
|
ndev->base_addr = (unsigned long)db->io_addr;
|
|
ndev->irq = db->irq_res->start;
|
|
|
|
/* ensure at least we have a default set of IO routines */
|
|
dm9000_set_io(db, iosize);
|
|
|
|
/* check to see if anything is being over-ridden */
|
|
if (pdata != NULL) {
|
|
/* check to see if the driver wants to over-ride the
|
|
* default IO width */
|
|
|
|
if (pdata->flags & DM9000_PLATF_8BITONLY)
|
|
dm9000_set_io(db, 1);
|
|
|
|
if (pdata->flags & DM9000_PLATF_16BITONLY)
|
|
dm9000_set_io(db, 2);
|
|
|
|
if (pdata->flags & DM9000_PLATF_32BITONLY)
|
|
dm9000_set_io(db, 4);
|
|
|
|
/* check to see if there are any IO routine
|
|
* over-rides */
|
|
|
|
if (pdata->inblk != NULL)
|
|
db->inblk = pdata->inblk;
|
|
|
|
if (pdata->outblk != NULL)
|
|
db->outblk = pdata->outblk;
|
|
|
|
if (pdata->dumpblk != NULL)
|
|
db->dumpblk = pdata->dumpblk;
|
|
|
|
db->flags = pdata->flags;
|
|
}
|
|
|
|
#ifdef CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL
|
|
db->flags |= DM9000_PLATF_SIMPLE_PHY;
|
|
#endif
|
|
|
|
dm9000_reset(db);
|
|
|
|
/* try multiple times, DM9000 sometimes gets the read wrong */
|
|
for (i = 0; i < 8; i++) {
|
|
id_val = ior(db, DM9000_VIDL);
|
|
id_val |= (u32)ior(db, DM9000_VIDH) << 8;
|
|
id_val |= (u32)ior(db, DM9000_PIDL) << 16;
|
|
id_val |= (u32)ior(db, DM9000_PIDH) << 24;
|
|
|
|
if (id_val == DM9000_ID)
|
|
break;
|
|
dev_err(db->dev, "read wrong id 0x%08x\n", id_val);
|
|
}
|
|
|
|
if (id_val != DM9000_ID) {
|
|
dev_err(db->dev, "wrong id: 0x%08x\n", id_val);
|
|
ret = -ENODEV;
|
|
goto out;
|
|
}
|
|
|
|
/* Identify what type of DM9000 we are working on */
|
|
|
|
id_val = ior(db, DM9000_CHIPR);
|
|
dev_dbg(db->dev, "dm9000 revision 0x%02x\n", id_val);
|
|
|
|
switch (id_val) {
|
|
case CHIPR_DM9000A:
|
|
db->type = TYPE_DM9000A;
|
|
break;
|
|
case CHIPR_DM9000B:
|
|
db->type = TYPE_DM9000B;
|
|
break;
|
|
default:
|
|
dev_dbg(db->dev, "ID %02x => defaulting to DM9000E\n", id_val);
|
|
db->type = TYPE_DM9000E;
|
|
}
|
|
|
|
/* dm9000a/b are capable of hardware checksum offload */
|
|
if (db->type == TYPE_DM9000A || db->type == TYPE_DM9000B) {
|
|
db->can_csum = 1;
|
|
db->rx_csum = 1;
|
|
ndev->features |= NETIF_F_IP_CSUM;
|
|
}
|
|
|
|
/* from this point we assume that we have found a DM9000 */
|
|
|
|
/* driver system function */
|
|
ether_setup(ndev);
|
|
|
|
ndev->netdev_ops = &dm9000_netdev_ops;
|
|
ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
|
|
ndev->ethtool_ops = &dm9000_ethtool_ops;
|
|
|
|
db->msg_enable = NETIF_MSG_LINK;
|
|
db->mii.phy_id_mask = 0x1f;
|
|
db->mii.reg_num_mask = 0x1f;
|
|
db->mii.force_media = 0;
|
|
db->mii.full_duplex = 0;
|
|
db->mii.dev = ndev;
|
|
db->mii.mdio_read = dm9000_phy_read;
|
|
db->mii.mdio_write = dm9000_phy_write;
|
|
|
|
mac_src = "eeprom";
|
|
|
|
/* try reading the node address from the attached EEPROM */
|
|
for (i = 0; i < 6; i += 2)
|
|
dm9000_read_eeprom(db, i / 2, ndev->dev_addr+i);
|
|
|
|
if (!is_valid_ether_addr(ndev->dev_addr) && pdata != NULL) {
|
|
mac_src = "platform data";
|
|
memcpy(ndev->dev_addr, pdata->dev_addr, 6);
|
|
}
|
|
|
|
if (!is_valid_ether_addr(ndev->dev_addr)) {
|
|
/* try reading from mac */
|
|
|
|
mac_src = "chip";
|
|
for (i = 0; i < 6; i++)
|
|
ndev->dev_addr[i] = ior(db, i+DM9000_PAR);
|
|
}
|
|
|
|
if (!is_valid_ether_addr(ndev->dev_addr))
|
|
dev_warn(db->dev, "%s: Invalid ethernet MAC address. Please "
|
|
"set using ifconfig\n", ndev->name);
|
|
|
|
platform_set_drvdata(pdev, ndev);
|
|
ret = register_netdev(ndev);
|
|
|
|
if (ret == 0)
|
|
printk(KERN_INFO "%s: dm9000%c at %p,%p IRQ %d MAC: %pM (%s)\n",
|
|
ndev->name, dm9000_type_to_char(db->type),
|
|
db->io_addr, db->io_data, ndev->irq,
|
|
ndev->dev_addr, mac_src);
|
|
return 0;
|
|
|
|
out:
|
|
dev_err(db->dev, "not found (%d).\n", ret);
|
|
|
|
dm9000_release_board(pdev, db);
|
|
free_netdev(ndev);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int
|
|
dm9000_drv_suspend(struct device *dev)
|
|
{
|
|
struct platform_device *pdev = to_platform_device(dev);
|
|
struct net_device *ndev = platform_get_drvdata(pdev);
|
|
board_info_t *db;
|
|
|
|
if (ndev) {
|
|
db = netdev_priv(ndev);
|
|
db->in_suspend = 1;
|
|
|
|
if (!netif_running(ndev))
|
|
return 0;
|
|
|
|
netif_device_detach(ndev);
|
|
|
|
/* only shutdown if not using WoL */
|
|
if (!db->wake_state)
|
|
dm9000_shutdown(ndev);
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
dm9000_drv_resume(struct device *dev)
|
|
{
|
|
struct platform_device *pdev = to_platform_device(dev);
|
|
struct net_device *ndev = platform_get_drvdata(pdev);
|
|
board_info_t *db = netdev_priv(ndev);
|
|
|
|
if (ndev) {
|
|
if (netif_running(ndev)) {
|
|
/* reset if we were not in wake mode to ensure if
|
|
* the device was powered off it is in a known state */
|
|
if (!db->wake_state) {
|
|
dm9000_reset(db);
|
|
dm9000_init_dm9000(ndev);
|
|
}
|
|
|
|
netif_device_attach(ndev);
|
|
}
|
|
|
|
db->in_suspend = 0;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static const struct dev_pm_ops dm9000_drv_pm_ops = {
|
|
.suspend = dm9000_drv_suspend,
|
|
.resume = dm9000_drv_resume,
|
|
};
|
|
|
|
static int __devexit
|
|
dm9000_drv_remove(struct platform_device *pdev)
|
|
{
|
|
struct net_device *ndev = platform_get_drvdata(pdev);
|
|
|
|
platform_set_drvdata(pdev, NULL);
|
|
|
|
unregister_netdev(ndev);
|
|
dm9000_release_board(pdev, (board_info_t *) netdev_priv(ndev));
|
|
free_netdev(ndev); /* free device structure */
|
|
|
|
dev_dbg(&pdev->dev, "released and freed device\n");
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver dm9000_driver = {
|
|
.driver = {
|
|
.name = "dm9000",
|
|
.owner = THIS_MODULE,
|
|
.pm = &dm9000_drv_pm_ops,
|
|
},
|
|
.probe = dm9000_probe,
|
|
.remove = __devexit_p(dm9000_drv_remove),
|
|
};
|
|
|
|
static int __init
|
|
dm9000_init(void)
|
|
{
|
|
printk(KERN_INFO "%s Ethernet Driver, V%s\n", CARDNAME, DRV_VERSION);
|
|
|
|
return platform_driver_register(&dm9000_driver);
|
|
}
|
|
|
|
static void __exit
|
|
dm9000_cleanup(void)
|
|
{
|
|
platform_driver_unregister(&dm9000_driver);
|
|
}
|
|
|
|
module_init(dm9000_init);
|
|
module_exit(dm9000_cleanup);
|
|
|
|
MODULE_AUTHOR("Sascha Hauer, Ben Dooks");
|
|
MODULE_DESCRIPTION("Davicom DM9000 network driver");
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_ALIAS("platform:dm9000");
|