2799bba69a
The namespace of NVKM is being changed to nvkm_ instead of nouveau_, which will be used for the DRM part of the driver. This is being done in order to make it very clear as to what part of the driver a given symbol belongs to, and as a minor step towards splitting the DRM driver out to be able to stand on its own (for virt). Because there's already a large amount of churn here anyway, this is as good a time as any to also switch to NVIDIA's device and chipset naming to ease collaboration with them. A comparison of objdump disassemblies proves no code changes. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
59 lines
2 KiB
C
59 lines
2 KiB
C
/*
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* Copyright 2012 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include "priv.h"
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static int
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gk104_ltc_init(struct nvkm_object *object)
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{
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struct nvkm_ltc_priv *priv = (void *)object;
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u32 lpg128 = !(nv_rd32(priv, 0x100c80) & 0x00000001);
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int ret;
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ret = nvkm_ltc_init(priv);
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if (ret)
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return ret;
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nv_wr32(priv, 0x17e8d8, priv->ltc_nr);
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nv_wr32(priv, 0x17e000, priv->ltc_nr);
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nv_wr32(priv, 0x17e8d4, priv->tag_base);
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nv_mask(priv, 0x17e8c0, 0x00000002, lpg128 ? 0x00000002 : 0x00000000);
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return 0;
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}
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struct nvkm_oclass *
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gk104_ltc_oclass = &(struct nvkm_ltc_impl) {
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.base.handle = NV_SUBDEV(LTC, 0xe4),
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.base.ofuncs = &(struct nvkm_ofuncs) {
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.ctor = gf100_ltc_ctor,
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.dtor = gf100_ltc_dtor,
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.init = gk104_ltc_init,
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.fini = _nvkm_ltc_fini,
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},
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.intr = gf100_ltc_intr,
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.cbc_clear = gf100_ltc_cbc_clear,
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.cbc_wait = gf100_ltc_cbc_wait,
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.zbc = 16,
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.zbc_clear_color = gf100_ltc_zbc_clear_color,
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.zbc_clear_depth = gf100_ltc_zbc_clear_depth,
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}.base;
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