eaecf0326f
Having a RAM device does not make sense for chips like GK20A which have no dedicated video memory. The dummy RAM device that we used so far works as a temporary band-aid, but in the longer term it is desirable for the driver to be able to work without any kind of VRAM. This patch adds a few conditionals in places where a RAM device was assumed to be present and allows some more objects to be allocated from the TT domain, allowing Nouveau to handle GPUs for which pfb->ram == NULL. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
244 lines
6.5 KiB
C
244 lines
6.5 KiB
C
/*
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* Copyright 2012 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include "priv.h"
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#include <core/enum.h>
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#include <subdev/fb.h>
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#include <subdev/timer.h>
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void
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gf100_ltc_cbc_clear(struct nvkm_ltc_priv *priv, u32 start, u32 limit)
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{
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nv_wr32(priv, 0x17e8cc, start);
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nv_wr32(priv, 0x17e8d0, limit);
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nv_wr32(priv, 0x17e8c8, 0x00000004);
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}
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void
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gf100_ltc_cbc_wait(struct nvkm_ltc_priv *priv)
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{
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int c, s;
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for (c = 0; c < priv->ltc_nr; c++) {
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for (s = 0; s < priv->lts_nr; s++)
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nv_wait(priv, 0x1410c8 + c * 0x2000 + s * 0x400, ~0, 0);
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}
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}
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void
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gf100_ltc_zbc_clear_color(struct nvkm_ltc_priv *priv, int i, const u32 color[4])
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{
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nv_mask(priv, 0x17ea44, 0x0000000f, i);
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nv_wr32(priv, 0x17ea48, color[0]);
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nv_wr32(priv, 0x17ea4c, color[1]);
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nv_wr32(priv, 0x17ea50, color[2]);
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nv_wr32(priv, 0x17ea54, color[3]);
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}
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void
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gf100_ltc_zbc_clear_depth(struct nvkm_ltc_priv *priv, int i, const u32 depth)
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{
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nv_mask(priv, 0x17ea44, 0x0000000f, i);
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nv_wr32(priv, 0x17ea58, depth);
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}
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static const struct nvkm_bitfield
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gf100_ltc_lts_intr_name[] = {
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{ 0x00000001, "IDLE_ERROR_IQ" },
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{ 0x00000002, "IDLE_ERROR_CBC" },
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{ 0x00000004, "IDLE_ERROR_TSTG" },
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{ 0x00000008, "IDLE_ERROR_DSTG" },
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{ 0x00000010, "EVICTED_CB" },
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{ 0x00000020, "ILLEGAL_COMPSTAT" },
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{ 0x00000040, "BLOCKLINEAR_CB" },
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{ 0x00000100, "ECC_SEC_ERROR" },
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{ 0x00000200, "ECC_DED_ERROR" },
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{ 0x00000400, "DEBUG" },
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{ 0x00000800, "ATOMIC_TO_Z" },
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{ 0x00001000, "ILLEGAL_ATOMIC" },
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{ 0x00002000, "BLKACTIVITY_ERR" },
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{}
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};
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static void
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gf100_ltc_lts_intr(struct nvkm_ltc_priv *priv, int ltc, int lts)
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{
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u32 base = 0x141000 + (ltc * 0x2000) + (lts * 0x400);
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u32 intr = nv_rd32(priv, base + 0x020);
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u32 stat = intr & 0x0000ffff;
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if (stat) {
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nv_info(priv, "LTC%d_LTS%d:", ltc, lts);
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nvkm_bitfield_print(gf100_ltc_lts_intr_name, stat);
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pr_cont("\n");
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}
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nv_wr32(priv, base + 0x020, intr);
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}
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void
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gf100_ltc_intr(struct nvkm_subdev *subdev)
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{
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struct nvkm_ltc_priv *priv = (void *)subdev;
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u32 mask;
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mask = nv_rd32(priv, 0x00017c);
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while (mask) {
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u32 lts, ltc = __ffs(mask);
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for (lts = 0; lts < priv->lts_nr; lts++)
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gf100_ltc_lts_intr(priv, ltc, lts);
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mask &= ~(1 << ltc);
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}
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}
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static int
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gf100_ltc_init(struct nvkm_object *object)
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{
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struct nvkm_ltc_priv *priv = (void *)object;
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u32 lpg128 = !(nv_rd32(priv, 0x100c80) & 0x00000001);
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int ret;
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ret = nvkm_ltc_init(priv);
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if (ret)
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return ret;
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nv_mask(priv, 0x17e820, 0x00100000, 0x00000000); /* INTR_EN &= ~0x10 */
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nv_wr32(priv, 0x17e8d8, priv->ltc_nr);
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nv_wr32(priv, 0x17e8d4, priv->tag_base);
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nv_mask(priv, 0x17e8c0, 0x00000002, lpg128 ? 0x00000002 : 0x00000000);
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return 0;
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}
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void
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gf100_ltc_dtor(struct nvkm_object *object)
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{
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struct nvkm_fb *pfb = nvkm_fb(object);
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struct nvkm_ltc_priv *priv = (void *)object;
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nvkm_mm_fini(&priv->tags);
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if (pfb->ram)
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nvkm_mm_free(&pfb->vram, &priv->tag_ram);
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nvkm_ltc_destroy(priv);
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}
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/* TODO: Figure out tag memory details and drop the over-cautious allocation.
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*/
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int
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gf100_ltc_init_tag_ram(struct nvkm_fb *pfb, struct nvkm_ltc_priv *priv)
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{
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u32 tag_size, tag_margin, tag_align;
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int ret;
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/* No VRAM, no tags for now. */
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if (!pfb->ram) {
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priv->num_tags = 0;
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goto mm_init;
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}
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/* tags for 1/4 of VRAM should be enough (8192/4 per GiB of VRAM) */
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priv->num_tags = (pfb->ram->size >> 17) / 4;
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if (priv->num_tags > (1 << 17))
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priv->num_tags = 1 << 17; /* we have 17 bits in PTE */
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priv->num_tags = (priv->num_tags + 63) & ~63; /* round up to 64 */
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tag_align = priv->ltc_nr * 0x800;
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tag_margin = (tag_align < 0x6000) ? 0x6000 : tag_align;
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/* 4 part 4 sub: 0x2000 bytes for 56 tags */
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/* 3 part 4 sub: 0x6000 bytes for 168 tags */
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/*
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* About 147 bytes per tag. Let's be safe and allocate x2, which makes
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* 0x4980 bytes for 64 tags, and round up to 0x6000 bytes for 64 tags.
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*
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* For 4 GiB of memory we'll have 8192 tags which makes 3 MiB, < 0.1 %.
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*/
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tag_size = (priv->num_tags / 64) * 0x6000 + tag_margin;
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tag_size += tag_align;
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tag_size = (tag_size + 0xfff) >> 12; /* round up */
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ret = nvkm_mm_tail(&pfb->vram, 1, 1, tag_size, tag_size, 1,
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&priv->tag_ram);
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if (ret) {
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priv->num_tags = 0;
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} else {
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u64 tag_base = ((u64)priv->tag_ram->offset << 12) + tag_margin;
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tag_base += tag_align - 1;
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ret = do_div(tag_base, tag_align);
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priv->tag_base = tag_base;
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}
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mm_init:
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ret = nvkm_mm_init(&priv->tags, 0, priv->num_tags, 1);
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return ret;
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}
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int
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gf100_ltc_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
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struct nvkm_oclass *oclass, void *data, u32 size,
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struct nvkm_object **pobject)
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{
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struct nvkm_fb *pfb = nvkm_fb(parent);
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struct nvkm_ltc_priv *priv;
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u32 parts, mask;
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int ret, i;
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ret = nvkm_ltc_create(parent, engine, oclass, &priv);
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*pobject = nv_object(priv);
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if (ret)
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return ret;
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parts = nv_rd32(priv, 0x022438);
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mask = nv_rd32(priv, 0x022554);
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for (i = 0; i < parts; i++) {
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if (!(mask & (1 << i)))
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priv->ltc_nr++;
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}
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priv->lts_nr = nv_rd32(priv, 0x17e8dc) >> 28;
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ret = gf100_ltc_init_tag_ram(pfb, priv);
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if (ret)
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return ret;
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nv_subdev(priv)->intr = gf100_ltc_intr;
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return 0;
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}
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struct nvkm_oclass *
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gf100_ltc_oclass = &(struct nvkm_ltc_impl) {
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.base.handle = NV_SUBDEV(LTC, 0xc0),
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.base.ofuncs = &(struct nvkm_ofuncs) {
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.ctor = gf100_ltc_ctor,
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.dtor = gf100_ltc_dtor,
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.init = gf100_ltc_init,
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.fini = _nvkm_ltc_fini,
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},
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.intr = gf100_ltc_intr,
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.cbc_clear = gf100_ltc_cbc_clear,
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.cbc_wait = gf100_ltc_cbc_wait,
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.zbc = 16,
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.zbc_clear_color = gf100_ltc_zbc_clear_color,
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.zbc_clear_depth = gf100_ltc_zbc_clear_depth,
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}.base;
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