78b2b4e76b
The namespace of NVKM is being changed to nvkm_ instead of nouveau_, which will be used for the DRM part of the driver. This is being done in order to make it very clear as to what part of the driver a given symbol belongs to, and as a minor step towards splitting the DRM driver out to be able to stand on its own (for virt). Because there's already a large amount of churn here anyway, this is as good a time as any to also switch to NVIDIA's device and chipset naming to ease collaboration with them. A comparison of objdump disassemblies proves no code changes. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
136 lines
4.3 KiB
C
136 lines
4.3 KiB
C
/*
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* Copyright 2012 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include "nv04.h"
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#include <core/ramht.h>
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#include <engine/gr/nv40.h>
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/******************************************************************************
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* instmem subdev implementation
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*****************************************************************************/
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static u32
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nv40_instmem_rd32(struct nvkm_object *object, u64 addr)
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{
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struct nv04_instmem_priv *priv = (void *)object;
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return ioread32_native(priv->iomem + addr);
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}
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static void
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nv40_instmem_wr32(struct nvkm_object *object, u64 addr, u32 data)
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{
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struct nv04_instmem_priv *priv = (void *)object;
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iowrite32_native(data, priv->iomem + addr);
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}
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static int
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nv40_instmem_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
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struct nvkm_oclass *oclass, void *data, u32 size,
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struct nvkm_object **pobject)
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{
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struct nvkm_device *device = nv_device(parent);
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struct nv04_instmem_priv *priv;
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int ret, bar, vs;
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ret = nvkm_instmem_create(parent, engine, oclass, &priv);
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*pobject = nv_object(priv);
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if (ret)
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return ret;
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/* map bar */
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if (nv_device_resource_len(device, 2))
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bar = 2;
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else
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bar = 3;
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priv->iomem = ioremap(nv_device_resource_start(device, bar),
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nv_device_resource_len(device, bar));
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if (!priv->iomem) {
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nv_error(priv, "unable to map PRAMIN BAR\n");
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return -EFAULT;
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}
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/* PRAMIN aperture maps over the end of vram, reserve enough space
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* to fit graphics contexts for every channel, the magics come
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* from engine/gr/nv40.c
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*/
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vs = hweight8((nv_rd32(priv, 0x001540) & 0x0000ff00) >> 8);
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if (device->chipset == 0x40) priv->base.reserved = 0x6aa0 * vs;
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else if (device->chipset < 0x43) priv->base.reserved = 0x4f00 * vs;
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else if (nv44_gr_class(priv)) priv->base.reserved = 0x4980 * vs;
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else priv->base.reserved = 0x4a40 * vs;
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priv->base.reserved += 16 * 1024;
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priv->base.reserved *= 32; /* per-channel */
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priv->base.reserved += 512 * 1024; /* pci(e)gart table */
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priv->base.reserved += 512 * 1024; /* object storage */
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priv->base.reserved = round_up(priv->base.reserved, 4096);
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ret = nvkm_mm_init(&priv->heap, 0, priv->base.reserved, 1);
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if (ret)
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return ret;
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/* 0x00000-0x10000: reserve for probable vbios image */
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ret = nvkm_gpuobj_new(nv_object(priv), NULL, 0x10000, 0, 0,
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&priv->vbios);
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if (ret)
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return ret;
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/* 0x10000-0x18000: reserve for RAMHT */
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ret = nvkm_ramht_new(nv_object(priv), NULL, 0x08000, 0, &priv->ramht);
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if (ret)
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return ret;
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/* 0x18000-0x18200: reserve for RAMRO
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* 0x18200-0x20000: padding
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*/
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ret = nvkm_gpuobj_new(nv_object(priv), NULL, 0x08000, 0, 0,
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&priv->ramro);
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if (ret)
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return ret;
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/* 0x20000-0x21000: reserve for RAMFC
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* 0x21000-0x40000: padding and some unknown crap
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*/
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ret = nvkm_gpuobj_new(nv_object(priv), NULL, 0x20000, 0,
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NVOBJ_FLAG_ZERO_ALLOC, &priv->ramfc);
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if (ret)
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return ret;
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return 0;
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}
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struct nvkm_oclass *
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nv40_instmem_oclass = &(struct nvkm_instmem_impl) {
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.base.handle = NV_SUBDEV(INSTMEM, 0x40),
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.base.ofuncs = &(struct nvkm_ofuncs) {
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.ctor = nv40_instmem_ctor,
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.dtor = nv04_instmem_dtor,
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.init = _nvkm_instmem_init,
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.fini = _nvkm_instmem_fini,
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.rd32 = nv40_instmem_rd32,
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.wr32 = nv40_instmem_wr32,
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},
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.instobj = &nv04_instobj_oclass.base,
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}.base;
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