4259460009
The namespace of NVKM is being changed to nvkm_ instead of nouveau_, which will be used for the DRM part of the driver. This is being done in order to make it very clear as to what part of the driver a given symbol belongs to, and as a minor step towards splitting the DRM driver out to be able to stand on its own (for virt). Because there's already a large amount of churn here anyway, this is as good a time as any to also switch to NVIDIA's device and chipset naming to ease collaboration with them. A comparison of objdump disassemblies proves no code changes. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
320 lines
9 KiB
C
320 lines
9 KiB
C
/*
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* Copyright 2012 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include "nv50.h"
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#include <core/client.h>
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#include <core/device.h>
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#include <core/engctx.h>
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#include <core/enum.h>
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int
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nv50_fb_memtype[0x80] = {
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1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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1, 1, 1, 1, 0, 0, 0, 0, 2, 2, 2, 2, 0, 0, 0, 0,
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1, 1, 1, 1, 1, 1, 1, 0, 2, 2, 2, 2, 2, 2, 2, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 0, 0,
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0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 2, 2, 2, 2,
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1, 0, 2, 0, 1, 0, 2, 0, 1, 1, 2, 2, 1, 1, 0, 0
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};
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bool
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nv50_fb_memtype_valid(struct nvkm_fb *pfb, u32 memtype)
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{
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return nv50_fb_memtype[(memtype & 0xff00) >> 8] != 0;
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}
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static const struct nvkm_enum vm_dispatch_subclients[] = {
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{ 0x00000000, "GRCTX", NULL },
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{ 0x00000001, "NOTIFY", NULL },
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{ 0x00000002, "QUERY", NULL },
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{ 0x00000003, "COND", NULL },
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{ 0x00000004, "M2M_IN", NULL },
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{ 0x00000005, "M2M_OUT", NULL },
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{ 0x00000006, "M2M_NOTIFY", NULL },
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{}
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};
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static const struct nvkm_enum vm_ccache_subclients[] = {
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{ 0x00000000, "CB", NULL },
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{ 0x00000001, "TIC", NULL },
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{ 0x00000002, "TSC", NULL },
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{}
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};
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static const struct nvkm_enum vm_prop_subclients[] = {
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{ 0x00000000, "RT0", NULL },
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{ 0x00000001, "RT1", NULL },
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{ 0x00000002, "RT2", NULL },
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{ 0x00000003, "RT3", NULL },
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{ 0x00000004, "RT4", NULL },
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{ 0x00000005, "RT5", NULL },
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{ 0x00000006, "RT6", NULL },
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{ 0x00000007, "RT7", NULL },
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{ 0x00000008, "ZETA", NULL },
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{ 0x00000009, "LOCAL", NULL },
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{ 0x0000000a, "GLOBAL", NULL },
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{ 0x0000000b, "STACK", NULL },
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{ 0x0000000c, "DST2D", NULL },
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{}
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};
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static const struct nvkm_enum vm_pfifo_subclients[] = {
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{ 0x00000000, "PUSHBUF", NULL },
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{ 0x00000001, "SEMAPHORE", NULL },
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{}
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};
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static const struct nvkm_enum vm_bar_subclients[] = {
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{ 0x00000000, "FB", NULL },
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{ 0x00000001, "IN", NULL },
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{}
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};
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static const struct nvkm_enum vm_client[] = {
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{ 0x00000000, "STRMOUT", NULL },
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{ 0x00000003, "DISPATCH", vm_dispatch_subclients },
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{ 0x00000004, "PFIFO_WRITE", NULL },
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{ 0x00000005, "CCACHE", vm_ccache_subclients },
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{ 0x00000006, "PMSPPP", NULL },
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{ 0x00000007, "CLIPID", NULL },
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{ 0x00000008, "PFIFO_READ", NULL },
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{ 0x00000009, "VFETCH", NULL },
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{ 0x0000000a, "TEXTURE", NULL },
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{ 0x0000000b, "PROP", vm_prop_subclients },
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{ 0x0000000c, "PVP", NULL },
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{ 0x0000000d, "PBSP", NULL },
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{ 0x0000000e, "PCRYPT", NULL },
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{ 0x0000000f, "PCOUNTER", NULL },
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{ 0x00000011, "PDAEMON", NULL },
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{}
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};
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static const struct nvkm_enum vm_engine[] = {
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{ 0x00000000, "PGRAPH", NULL, NVDEV_ENGINE_GR },
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{ 0x00000001, "PVP", NULL, NVDEV_ENGINE_VP },
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{ 0x00000004, "PEEPHOLE", NULL },
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{ 0x00000005, "PFIFO", vm_pfifo_subclients, NVDEV_ENGINE_FIFO },
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{ 0x00000006, "BAR", vm_bar_subclients },
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{ 0x00000008, "PMSPPP", NULL, NVDEV_ENGINE_MSPPP },
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{ 0x00000008, "PMPEG", NULL, NVDEV_ENGINE_MPEG },
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{ 0x00000009, "PBSP", NULL, NVDEV_ENGINE_BSP },
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{ 0x0000000a, "PCRYPT", NULL, NVDEV_ENGINE_CIPHER },
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{ 0x0000000b, "PCOUNTER", NULL },
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{ 0x0000000c, "SEMAPHORE_BG", NULL },
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{ 0x0000000d, "PCE0", NULL, NVDEV_ENGINE_CE0 },
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{ 0x0000000e, "PDAEMON", NULL },
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{}
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};
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static const struct nvkm_enum vm_fault[] = {
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{ 0x00000000, "PT_NOT_PRESENT", NULL },
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{ 0x00000001, "PT_TOO_SHORT", NULL },
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{ 0x00000002, "PAGE_NOT_PRESENT", NULL },
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{ 0x00000003, "PAGE_SYSTEM_ONLY", NULL },
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{ 0x00000004, "PAGE_READ_ONLY", NULL },
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{ 0x00000006, "NULL_DMAOBJ", NULL },
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{ 0x00000007, "WRONG_MEMTYPE", NULL },
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{ 0x0000000b, "VRAM_LIMIT", NULL },
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{ 0x0000000f, "DMAOBJ_LIMIT", NULL },
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{}
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};
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static void
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nv50_fb_intr(struct nvkm_subdev *subdev)
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{
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struct nvkm_device *device = nv_device(subdev);
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struct nvkm_engine *engine;
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struct nv50_fb_priv *priv = (void *)subdev;
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const struct nvkm_enum *en, *cl;
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struct nvkm_object *engctx = NULL;
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u32 trap[6], idx, chan;
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u8 st0, st1, st2, st3;
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int i;
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idx = nv_rd32(priv, 0x100c90);
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if (!(idx & 0x80000000))
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return;
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idx &= 0x00ffffff;
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for (i = 0; i < 6; i++) {
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nv_wr32(priv, 0x100c90, idx | i << 24);
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trap[i] = nv_rd32(priv, 0x100c94);
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}
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nv_wr32(priv, 0x100c90, idx | 0x80000000);
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/* decode status bits into something more useful */
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if (device->chipset < 0xa3 ||
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device->chipset == 0xaa || device->chipset == 0xac) {
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st0 = (trap[0] & 0x0000000f) >> 0;
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st1 = (trap[0] & 0x000000f0) >> 4;
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st2 = (trap[0] & 0x00000f00) >> 8;
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st3 = (trap[0] & 0x0000f000) >> 12;
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} else {
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st0 = (trap[0] & 0x000000ff) >> 0;
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st1 = (trap[0] & 0x0000ff00) >> 8;
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st2 = (trap[0] & 0x00ff0000) >> 16;
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st3 = (trap[0] & 0xff000000) >> 24;
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}
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chan = (trap[2] << 16) | trap[1];
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en = nvkm_enum_find(vm_engine, st0);
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if (en && en->data2) {
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const struct nvkm_enum *orig_en = en;
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while (en->name && en->value == st0 && en->data2) {
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engine = nvkm_engine(subdev, en->data2);
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/*XXX: clean this up */
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if (!engine && en->data2 == NVDEV_ENGINE_BSP)
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engine = nvkm_engine(subdev, NVDEV_ENGINE_MSVLD);
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if (!engine && en->data2 == NVDEV_ENGINE_CIPHER)
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engine = nvkm_engine(subdev, NVDEV_ENGINE_SEC);
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if (!engine && en->data2 == NVDEV_ENGINE_VP)
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engine = nvkm_engine(subdev, NVDEV_ENGINE_MSPDEC);
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if (engine) {
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engctx = nvkm_engctx_get(engine, chan);
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if (engctx)
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break;
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}
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en++;
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}
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if (!engctx)
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en = orig_en;
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}
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nv_error(priv, "trapped %s at 0x%02x%04x%04x on channel 0x%08x [%s] ",
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(trap[5] & 0x00000100) ? "read" : "write",
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trap[5] & 0xff, trap[4] & 0xffff, trap[3] & 0xffff, chan,
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nvkm_client_name(engctx));
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nvkm_engctx_put(engctx);
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if (en)
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pr_cont("%s/", en->name);
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else
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pr_cont("%02x/", st0);
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cl = nvkm_enum_find(vm_client, st2);
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if (cl)
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pr_cont("%s/", cl->name);
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else
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pr_cont("%02x/", st2);
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if (cl && cl->data) cl = nvkm_enum_find(cl->data, st3);
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else if (en && en->data) cl = nvkm_enum_find(en->data, st3);
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else cl = NULL;
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if (cl)
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pr_cont("%s", cl->name);
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else
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pr_cont("%02x", st3);
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pr_cont(" reason: ");
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en = nvkm_enum_find(vm_fault, st1);
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if (en)
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pr_cont("%s\n", en->name);
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else
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pr_cont("0x%08x\n", st1);
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}
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int
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nv50_fb_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
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struct nvkm_oclass *oclass, void *data, u32 size,
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struct nvkm_object **pobject)
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{
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struct nvkm_device *device = nv_device(parent);
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struct nv50_fb_priv *priv;
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int ret;
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ret = nvkm_fb_create(parent, engine, oclass, &priv);
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*pobject = nv_object(priv);
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if (ret)
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return ret;
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priv->r100c08_page = alloc_page(GFP_KERNEL | __GFP_ZERO);
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if (priv->r100c08_page) {
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priv->r100c08 = dma_map_page(nv_device_base(device),
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priv->r100c08_page, 0, PAGE_SIZE,
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DMA_BIDIRECTIONAL);
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if (dma_mapping_error(nv_device_base(device), priv->r100c08))
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return -EFAULT;
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} else {
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nv_warn(priv, "failed 0x100c08 page alloc\n");
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}
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nv_subdev(priv)->intr = nv50_fb_intr;
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return 0;
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}
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void
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nv50_fb_dtor(struct nvkm_object *object)
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{
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struct nvkm_device *device = nv_device(object);
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struct nv50_fb_priv *priv = (void *)object;
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if (priv->r100c08_page) {
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dma_unmap_page(nv_device_base(device), priv->r100c08, PAGE_SIZE,
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DMA_BIDIRECTIONAL);
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__free_page(priv->r100c08_page);
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}
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nvkm_fb_destroy(&priv->base);
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}
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int
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nv50_fb_init(struct nvkm_object *object)
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{
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struct nv50_fb_impl *impl = (void *)object->oclass;
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struct nv50_fb_priv *priv = (void *)object;
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int ret;
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ret = nvkm_fb_init(&priv->base);
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if (ret)
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return ret;
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/* Not a clue what this is exactly. Without pointing it at a
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* scratch page, VRAM->GART blits with M2MF (as in DDX DFS)
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* cause IOMMU "read from address 0" errors (rh#561267)
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*/
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nv_wr32(priv, 0x100c08, priv->r100c08 >> 8);
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/* This is needed to get meaningful information from 100c90
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* on traps. No idea what these values mean exactly. */
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nv_wr32(priv, 0x100c90, impl->trap);
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return 0;
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}
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struct nvkm_oclass *
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nv50_fb_oclass = &(struct nv50_fb_impl) {
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.base.base.handle = NV_SUBDEV(FB, 0x50),
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.base.base.ofuncs = &(struct nvkm_ofuncs) {
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.ctor = nv50_fb_ctor,
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.dtor = nv50_fb_dtor,
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.init = nv50_fb_init,
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.fini = _nvkm_fb_fini,
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},
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.base.memtype = nv50_fb_memtype_valid,
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.base.ram = &nv50_ram_oclass,
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.trap = 0x000707ff,
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}.base.base;
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