5f8824de8a
The namespace of NVKM is being changed to nvkm_ instead of nouveau_, which will be used for the DRM part of the driver. This is being done in order to make it very clear as to what part of the driver a given symbol belongs to, and as a minor step towards splitting the DRM driver out to be able to stand on its own (for virt). Because there's already a large amount of churn here anyway, this is as good a time as any to also switch to NVIDIA's device and chipset naming to ease collaboration with them. A comparison of objdump disassemblies proves no code changes. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
104 lines
3 KiB
C
104 lines
3 KiB
C
/*
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* Copyright 2012 Nouveau Community
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Martin Peres <martin.peres@labri.fr>
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* Ben Skeggs
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*/
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#include "nv04.h"
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#include <subdev/timer.h>
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static int
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nv50_bus_hwsq_exec(struct nvkm_bus *pbus, u32 *data, u32 size)
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{
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struct nv50_bus_priv *priv = (void *)pbus;
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int i;
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nv_mask(pbus, 0x001098, 0x00000008, 0x00000000);
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nv_wr32(pbus, 0x001304, 0x00000000);
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for (i = 0; i < size; i++)
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nv_wr32(priv, 0x001400 + (i * 4), data[i]);
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nv_mask(pbus, 0x001098, 0x00000018, 0x00000018);
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nv_wr32(pbus, 0x00130c, 0x00000003);
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return nv_wait(pbus, 0x001308, 0x00000100, 0x00000000) ? 0 : -ETIMEDOUT;
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}
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void
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nv50_bus_intr(struct nvkm_subdev *subdev)
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{
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struct nvkm_bus *pbus = nvkm_bus(subdev);
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u32 stat = nv_rd32(pbus, 0x001100) & nv_rd32(pbus, 0x001140);
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if (stat & 0x00000008) {
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u32 addr = nv_rd32(pbus, 0x009084);
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u32 data = nv_rd32(pbus, 0x009088);
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nv_error(pbus, "MMIO %s of 0x%08x FAULT at 0x%06x\n",
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(addr & 0x00000002) ? "write" : "read", data,
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(addr & 0x00fffffc));
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stat &= ~0x00000008;
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nv_wr32(pbus, 0x001100, 0x00000008);
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}
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if (stat & 0x00010000) {
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subdev = nvkm_subdev(pbus, NVDEV_SUBDEV_THERM);
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if (subdev && subdev->intr)
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subdev->intr(subdev);
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stat &= ~0x00010000;
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nv_wr32(pbus, 0x001100, 0x00010000);
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}
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if (stat) {
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nv_error(pbus, "unknown intr 0x%08x\n", stat);
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nv_mask(pbus, 0x001140, stat, 0);
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}
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}
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int
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nv50_bus_init(struct nvkm_object *object)
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{
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struct nv04_bus_priv *priv = (void *)object;
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int ret;
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ret = nvkm_bus_init(&priv->base);
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if (ret)
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return ret;
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nv_wr32(priv, 0x001100, 0xffffffff);
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nv_wr32(priv, 0x001140, 0x00010008);
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return 0;
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}
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struct nvkm_oclass *
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nv50_bus_oclass = &(struct nv04_bus_impl) {
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.base.handle = NV_SUBDEV(BUS, 0x50),
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.base.ofuncs = &(struct nvkm_ofuncs) {
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.ctor = nv04_bus_ctor,
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.dtor = _nvkm_bus_dtor,
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.init = nv50_bus_init,
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.fini = _nvkm_bus_fini,
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},
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.intr = nv50_bus_intr,
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.hwsq_exec = nv50_bus_hwsq_exec,
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.hwsq_size = 64,
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}.base;
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