The namespace of NVKM is being changed to nvkm_ instead of nouveau_, which will be used for the DRM part of the driver. This is being done in order to make it very clear as to what part of the driver a given symbol belongs to, and as a minor step towards splitting the DRM driver out to be able to stand on its own (for virt). Because there's already a large amount of churn here anyway, this is as good a time as any to also switch to NVIDIA's device and chipset naming to ease collaboration with them. A comparison of objdump disassemblies proves no code changes. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
141 lines
4.4 KiB
C
141 lines
4.4 KiB
C
/*
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* Copyright 2012 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include "nv50.h"
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#include <subdev/bar.h>
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/*******************************************************************************
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* software object classes
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******************************************************************************/
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static int
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gf100_sw_mthd_vblsem_offset(struct nvkm_object *object, u32 mthd,
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void *args, u32 size)
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{
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struct nv50_sw_chan *chan = (void *)nv_engctx(object->parent);
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u64 data = *(u32 *)args;
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if (mthd == 0x0400) {
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chan->vblank.offset &= 0x00ffffffffULL;
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chan->vblank.offset |= data << 32;
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} else {
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chan->vblank.offset &= 0xff00000000ULL;
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chan->vblank.offset |= data;
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}
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return 0;
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}
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static int
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gf100_sw_mthd_mp_control(struct nvkm_object *object, u32 mthd,
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void *args, u32 size)
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{
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struct nv50_sw_chan *chan = (void *)nv_engctx(object->parent);
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struct nv50_sw_priv *priv = (void *)nv_object(chan)->engine;
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u32 data = *(u32 *)args;
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switch (mthd) {
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case 0x600:
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nv_wr32(priv, 0x419e00, data); /* MP.PM_UNK000 */
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break;
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case 0x644:
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if (data & ~0x1ffffe)
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return -EINVAL;
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nv_wr32(priv, 0x419e44, data); /* MP.TRAP_WARP_ERROR_EN */
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break;
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case 0x6ac:
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nv_wr32(priv, 0x419eac, data); /* MP.PM_UNK0AC */
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static struct nvkm_omthds
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gf100_sw_omthds[] = {
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{ 0x0400, 0x0400, gf100_sw_mthd_vblsem_offset },
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{ 0x0404, 0x0404, gf100_sw_mthd_vblsem_offset },
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{ 0x0408, 0x0408, nv50_sw_mthd_vblsem_value },
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{ 0x040c, 0x040c, nv50_sw_mthd_vblsem_release },
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{ 0x0500, 0x0500, nv50_sw_mthd_flip },
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{ 0x0600, 0x0600, gf100_sw_mthd_mp_control },
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{ 0x0644, 0x0644, gf100_sw_mthd_mp_control },
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{ 0x06ac, 0x06ac, gf100_sw_mthd_mp_control },
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{}
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};
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static struct nvkm_oclass
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gf100_sw_sclass[] = {
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{ 0x906e, &nvkm_object_ofuncs, gf100_sw_omthds },
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{}
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};
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/*******************************************************************************
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* software context
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******************************************************************************/
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static int
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gf100_sw_vblsem_release(struct nvkm_notify *notify)
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{
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struct nv50_sw_chan *chan =
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container_of(notify, typeof(*chan), vblank.notify[notify->index]);
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struct nv50_sw_priv *priv = (void *)nv_object(chan)->engine;
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struct nvkm_bar *bar = nvkm_bar(priv);
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nv_wr32(priv, 0x001718, 0x80000000 | chan->vblank.channel);
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bar->flush(bar);
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nv_wr32(priv, 0x06000c, upper_32_bits(chan->vblank.offset));
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nv_wr32(priv, 0x060010, lower_32_bits(chan->vblank.offset));
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nv_wr32(priv, 0x060014, chan->vblank.value);
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return NVKM_NOTIFY_DROP;
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}
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static struct nv50_sw_cclass
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gf100_sw_cclass = {
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.base.handle = NV_ENGCTX(SW, 0xc0),
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.base.ofuncs = &(struct nvkm_ofuncs) {
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.ctor = nv50_sw_context_ctor,
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.dtor = nv50_sw_context_dtor,
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.init = _nvkm_sw_context_init,
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.fini = _nvkm_sw_context_fini,
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},
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.vblank = gf100_sw_vblsem_release,
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};
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/*******************************************************************************
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* software engine/subdev functions
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******************************************************************************/
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struct nvkm_oclass *
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gf100_sw_oclass = &(struct nv50_sw_oclass) {
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.base.handle = NV_ENGINE(SW, 0xc0),
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.base.ofuncs = &(struct nvkm_ofuncs) {
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.ctor = nv50_sw_ctor,
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.dtor = _nvkm_sw_dtor,
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.init = _nvkm_sw_init,
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.fini = _nvkm_sw_fini,
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},
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.cclass = &gf100_sw_cclass.base,
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.sclass = gf100_sw_sclass,
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}.base;
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