e3c71eb274
The namespace of NVKM is being changed to nvkm_ instead of nouveau_, which will be used for the DRM part of the driver. This is being done in order to make it very clear as to what part of the driver a given symbol belongs to, and as a minor step towards splitting the DRM driver out to be able to stand on its own (for virt). Because there's already a large amount of churn here anyway, this is as good a time as any to also switch to NVIDIA's device and chipset naming to ease collaboration with them. A comparison of objdump disassemblies proves no code changes. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
159 lines
4.9 KiB
C
159 lines
4.9 KiB
C
#include "nv20.h"
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#include "regs.h"
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#include <engine/fifo.h>
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/*******************************************************************************
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* Graphics object classes
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******************************************************************************/
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static struct nvkm_oclass
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nv35_gr_sclass[] = {
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{ 0x0012, &nv04_gr_ofuncs, NULL }, /* beta1 */
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{ 0x0019, &nv04_gr_ofuncs, NULL }, /* clip */
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{ 0x0030, &nv04_gr_ofuncs, NULL }, /* null */
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{ 0x0039, &nv04_gr_ofuncs, NULL }, /* m2mf */
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{ 0x0043, &nv04_gr_ofuncs, NULL }, /* rop */
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{ 0x0044, &nv04_gr_ofuncs, NULL }, /* patt */
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{ 0x004a, &nv04_gr_ofuncs, NULL }, /* gdi */
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{ 0x0062, &nv04_gr_ofuncs, NULL }, /* surf2d */
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{ 0x0072, &nv04_gr_ofuncs, NULL }, /* beta4 */
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{ 0x0089, &nv04_gr_ofuncs, NULL }, /* sifm */
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{ 0x008a, &nv04_gr_ofuncs, NULL }, /* ifc */
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{ 0x009f, &nv04_gr_ofuncs, NULL }, /* imageblit */
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{ 0x0362, &nv04_gr_ofuncs, NULL }, /* surf2d (nv30) */
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{ 0x0389, &nv04_gr_ofuncs, NULL }, /* sifm (nv30) */
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{ 0x038a, &nv04_gr_ofuncs, NULL }, /* ifc (nv30) */
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{ 0x039e, &nv04_gr_ofuncs, NULL }, /* swzsurf (nv30) */
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{ 0x0497, &nv04_gr_ofuncs, NULL }, /* rankine */
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{},
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};
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/*******************************************************************************
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* PGRAPH context
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******************************************************************************/
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static int
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nv35_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
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struct nvkm_oclass *oclass, void *data, u32 size,
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struct nvkm_object **pobject)
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{
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struct nv20_gr_chan *chan;
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int ret, i;
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ret = nvkm_gr_context_create(parent, engine, oclass, NULL, 0x577c,
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16, NVOBJ_FLAG_ZERO_ALLOC, &chan);
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*pobject = nv_object(chan);
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if (ret)
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return ret;
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chan->chid = nvkm_fifo_chan(parent)->chid;
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nv_wo32(chan, 0x0028, 0x00000001 | (chan->chid << 24));
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nv_wo32(chan, 0x040c, 0x00000101);
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nv_wo32(chan, 0x0420, 0x00000111);
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nv_wo32(chan, 0x0424, 0x00000060);
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nv_wo32(chan, 0x0440, 0x00000080);
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nv_wo32(chan, 0x0444, 0xffff0000);
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nv_wo32(chan, 0x0448, 0x00000001);
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nv_wo32(chan, 0x045c, 0x44400000);
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nv_wo32(chan, 0x0488, 0xffff0000);
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for (i = 0x04dc; i < 0x04e4; i += 4)
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nv_wo32(chan, i, 0x0fff0000);
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nv_wo32(chan, 0x04e8, 0x00011100);
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for (i = 0x0504; i < 0x0544; i += 4)
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nv_wo32(chan, i, 0x07ff0000);
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nv_wo32(chan, 0x054c, 0x4b7fffff);
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nv_wo32(chan, 0x0588, 0x00000080);
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nv_wo32(chan, 0x058c, 0x30201000);
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nv_wo32(chan, 0x0590, 0x70605040);
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nv_wo32(chan, 0x0594, 0xb8a89888);
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nv_wo32(chan, 0x0598, 0xf8e8d8c8);
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nv_wo32(chan, 0x05ac, 0xb0000000);
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for (i = 0x0604; i < 0x0644; i += 4)
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nv_wo32(chan, i, 0x00010588);
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for (i = 0x0644; i < 0x0684; i += 4)
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nv_wo32(chan, i, 0x00030303);
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for (i = 0x06c4; i < 0x0704; i += 4)
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nv_wo32(chan, i, 0x0008aae4);
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for (i = 0x0704; i < 0x0744; i += 4)
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nv_wo32(chan, i, 0x01012000);
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for (i = 0x0744; i < 0x0784; i += 4)
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nv_wo32(chan, i, 0x00080008);
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nv_wo32(chan, 0x0860, 0x00040000);
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nv_wo32(chan, 0x0864, 0x00010000);
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for (i = 0x0868; i < 0x0878; i += 4)
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nv_wo32(chan, i, 0x00040004);
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for (i = 0x1f1c; i <= 0x308c ; i += 16) {
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nv_wo32(chan, i + 0, 0x10700ff9);
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nv_wo32(chan, i + 4, 0x0436086c);
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nv_wo32(chan, i + 8, 0x000c001b);
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}
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for (i = 0x30bc; i < 0x30cc; i += 4)
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nv_wo32(chan, i, 0x0000ffff);
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nv_wo32(chan, 0x3450, 0x3f800000);
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nv_wo32(chan, 0x380c, 0x3f800000);
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nv_wo32(chan, 0x3820, 0x3f800000);
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nv_wo32(chan, 0x384c, 0x40000000);
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nv_wo32(chan, 0x3850, 0x3f800000);
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nv_wo32(chan, 0x3854, 0x3f000000);
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nv_wo32(chan, 0x385c, 0x40000000);
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nv_wo32(chan, 0x3860, 0x3f800000);
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nv_wo32(chan, 0x3868, 0xbf800000);
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nv_wo32(chan, 0x3870, 0xbf800000);
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return 0;
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}
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static struct nvkm_oclass
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nv35_gr_cclass = {
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.handle = NV_ENGCTX(GR, 0x35),
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.ofuncs = &(struct nvkm_ofuncs) {
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.ctor = nv35_gr_context_ctor,
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.dtor = _nvkm_gr_context_dtor,
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.init = nv20_gr_context_init,
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.fini = nv20_gr_context_fini,
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.rd32 = _nvkm_gr_context_rd32,
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.wr32 = _nvkm_gr_context_wr32,
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},
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};
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/*******************************************************************************
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* PGRAPH engine/subdev functions
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******************************************************************************/
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static int
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nv35_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
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struct nvkm_oclass *oclass, void *data, u32 size,
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struct nvkm_object **pobject)
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{
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struct nv20_gr_priv *priv;
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int ret;
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ret = nvkm_gr_create(parent, engine, oclass, true, &priv);
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*pobject = nv_object(priv);
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if (ret)
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return ret;
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ret = nvkm_gpuobj_new(nv_object(priv), NULL, 32 * 4, 16,
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NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab);
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if (ret)
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return ret;
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nv_subdev(priv)->unit = 0x00001000;
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nv_subdev(priv)->intr = nv20_gr_intr;
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nv_engine(priv)->cclass = &nv35_gr_cclass;
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nv_engine(priv)->sclass = nv35_gr_sclass;
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nv_engine(priv)->tile_prog = nv20_gr_tile_prog;
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return 0;
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}
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struct nvkm_oclass
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nv35_gr_oclass = {
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.handle = NV_ENGINE(GR, 0x35),
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.ofuncs = &(struct nvkm_ofuncs) {
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.ctor = nv35_gr_ctor,
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.dtor = nv20_gr_dtor,
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.init = nv30_gr_init,
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.fini = _nvkm_gr_fini,
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},
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};
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