The namespace of NVKM is being changed to nvkm_ instead of nouveau_, which will be used for the DRM part of the driver. This is being done in order to make it very clear as to what part of the driver a given symbol belongs to, and as a minor step towards splitting the DRM driver out to be able to stand on its own (for virt). Because there's already a large amount of churn here anyway, this is as good a time as any to also switch to NVIDIA's device and chipset naming to ease collaboration with them. A comparison of objdump disassemblies proves no code changes. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
164 lines
4.4 KiB
C
164 lines
4.4 KiB
C
/*
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* Copyright 2012 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include "priv.h"
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#include <core/client.h>
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#include <core/device.h>
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#include <subdev/fb.h>
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#include <subdev/instmem.h>
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#include <nvif/class.h>
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#include <nvif/unpack.h>
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static int
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nvkm_dmaobj_bind(struct nvkm_dmaobj *dmaobj, struct nvkm_object *parent,
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struct nvkm_gpuobj **pgpuobj)
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{
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const struct nvkm_dmaeng_impl *impl = (void *)
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nv_oclass(nv_object(dmaobj)->engine);
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int ret = 0;
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if (nv_object(dmaobj) == parent) { /* ctor bind */
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if (nv_mclass(parent->parent) == NV_DEVICE) {
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/* delayed, or no, binding */
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return 0;
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}
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ret = impl->bind(dmaobj, parent, pgpuobj);
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if (ret == 0)
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nvkm_object_ref(NULL, &parent);
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return ret;
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}
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return impl->bind(dmaobj, parent, pgpuobj);
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}
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int
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nvkm_dmaobj_create_(struct nvkm_object *parent,
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struct nvkm_object *engine,
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struct nvkm_oclass *oclass, void **pdata, u32 *psize,
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int length, void **pobject)
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{
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union {
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struct nv_dma_v0 v0;
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} *args = *pdata;
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struct nvkm_instmem *instmem = nvkm_instmem(parent);
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struct nvkm_client *client = nvkm_client(parent);
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struct nvkm_device *device = nv_device(parent);
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struct nvkm_fb *pfb = nvkm_fb(parent);
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struct nvkm_dmaobj *dmaobj;
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void *data = *pdata;
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u32 size = *psize;
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int ret;
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ret = nvkm_object_create_(parent, engine, oclass, 0, length, pobject);
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dmaobj = *pobject;
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if (ret)
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return ret;
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nv_ioctl(parent, "create dma size %d\n", *psize);
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if (nvif_unpack(args->v0, 0, 0, true)) {
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nv_ioctl(parent, "create dma vers %d target %d access %d "
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"start %016llx limit %016llx\n",
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args->v0.version, args->v0.target, args->v0.access,
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args->v0.start, args->v0.limit);
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dmaobj->target = args->v0.target;
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dmaobj->access = args->v0.access;
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dmaobj->start = args->v0.start;
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dmaobj->limit = args->v0.limit;
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} else
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return ret;
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*pdata = data;
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*psize = size;
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if (dmaobj->start > dmaobj->limit)
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return -EINVAL;
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switch (dmaobj->target) {
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case NV_DMA_V0_TARGET_VM:
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dmaobj->target = NV_MEM_TARGET_VM;
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break;
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case NV_DMA_V0_TARGET_VRAM:
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if (!client->super) {
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if (dmaobj->limit >= pfb->ram->size - instmem->reserved)
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return -EACCES;
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if (device->card_type >= NV_50)
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return -EACCES;
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}
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dmaobj->target = NV_MEM_TARGET_VRAM;
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break;
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case NV_DMA_V0_TARGET_PCI:
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if (!client->super)
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return -EACCES;
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dmaobj->target = NV_MEM_TARGET_PCI;
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break;
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case NV_DMA_V0_TARGET_PCI_US:
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case NV_DMA_V0_TARGET_AGP:
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if (!client->super)
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return -EACCES;
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dmaobj->target = NV_MEM_TARGET_PCI_NOSNOOP;
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break;
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default:
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return -EINVAL;
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}
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switch (dmaobj->access) {
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case NV_DMA_V0_ACCESS_VM:
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dmaobj->access = NV_MEM_ACCESS_VM;
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break;
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case NV_DMA_V0_ACCESS_RD:
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dmaobj->access = NV_MEM_ACCESS_RO;
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break;
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case NV_DMA_V0_ACCESS_WR:
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dmaobj->access = NV_MEM_ACCESS_WO;
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break;
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case NV_DMA_V0_ACCESS_RDWR:
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dmaobj->access = NV_MEM_ACCESS_RW;
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break;
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default:
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return -EINVAL;
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}
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return ret;
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}
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int
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_nvkm_dmaeng_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
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struct nvkm_oclass *oclass, void *data, u32 size,
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struct nvkm_object **pobject)
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{
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const struct nvkm_dmaeng_impl *impl = (void *)oclass;
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struct nvkm_dmaeng *dmaeng;
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int ret;
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ret = nvkm_engine_create(parent, engine, oclass, true, "DMAOBJ",
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"dmaobj", &dmaeng);
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*pobject = nv_object(dmaeng);
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if (ret)
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return ret;
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nv_engine(dmaeng)->sclass = impl->sclass;
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dmaeng->bind = nvkm_dmaobj_bind;
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return 0;
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}
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