878da15adb
The namespace of NVKM is being changed to nvkm_ instead of nouveau_, which will be used for the DRM part of the driver. This is being done in order to make it very clear as to what part of the driver a given symbol belongs to, and as a minor step towards splitting the DRM driver out to be able to stand on its own (for virt). Because there's already a large amount of churn here anyway, this is as good a time as any to also switch to NVIDIA's device and chipset naming to ease collaboration with them. A comparison of objdump disassemblies proves no code changes. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
272 lines
7.2 KiB
C
272 lines
7.2 KiB
C
/*
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* Copyright 2012 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include "nv50.h"
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#include <nvif/class.h>
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/*******************************************************************************
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* EVO master channel object
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******************************************************************************/
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const struct nv50_disp_mthd_list
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g84_disp_core_mthd_dac = {
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.mthd = 0x0080,
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.addr = 0x000008,
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.data = {
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{ 0x0400, 0x610b58 },
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{ 0x0404, 0x610bdc },
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{ 0x0420, 0x610bc4 },
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{}
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}
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};
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const struct nv50_disp_mthd_list
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g84_disp_core_mthd_head = {
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.mthd = 0x0400,
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.addr = 0x000540,
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.data = {
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{ 0x0800, 0x610ad8 },
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{ 0x0804, 0x610ad0 },
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{ 0x0808, 0x610a48 },
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{ 0x080c, 0x610a78 },
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{ 0x0810, 0x610ac0 },
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{ 0x0814, 0x610af8 },
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{ 0x0818, 0x610b00 },
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{ 0x081c, 0x610ae8 },
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{ 0x0820, 0x610af0 },
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{ 0x0824, 0x610b08 },
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{ 0x0828, 0x610b10 },
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{ 0x082c, 0x610a68 },
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{ 0x0830, 0x610a60 },
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{ 0x0834, 0x000000 },
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{ 0x0838, 0x610a40 },
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{ 0x0840, 0x610a24 },
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{ 0x0844, 0x610a2c },
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{ 0x0848, 0x610aa8 },
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{ 0x084c, 0x610ab0 },
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{ 0x085c, 0x610c5c },
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{ 0x0860, 0x610a84 },
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{ 0x0864, 0x610a90 },
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{ 0x0868, 0x610b18 },
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{ 0x086c, 0x610b20 },
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{ 0x0870, 0x610ac8 },
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{ 0x0874, 0x610a38 },
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{ 0x0878, 0x610c50 },
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{ 0x0880, 0x610a58 },
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{ 0x0884, 0x610a9c },
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{ 0x089c, 0x610c68 },
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{ 0x08a0, 0x610a70 },
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{ 0x08a4, 0x610a50 },
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{ 0x08a8, 0x610ae0 },
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{ 0x08c0, 0x610b28 },
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{ 0x08c4, 0x610b30 },
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{ 0x08c8, 0x610b40 },
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{ 0x08d4, 0x610b38 },
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{ 0x08d8, 0x610b48 },
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{ 0x08dc, 0x610b50 },
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{ 0x0900, 0x610a18 },
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{ 0x0904, 0x610ab8 },
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{ 0x0910, 0x610c70 },
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{ 0x0914, 0x610c78 },
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{}
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}
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};
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const struct nv50_disp_mthd_chan
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g84_disp_core_mthd_chan = {
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.name = "Core",
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.addr = 0x000000,
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.data = {
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{ "Global", 1, &nv50_disp_core_mthd_base },
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{ "DAC", 3, &g84_disp_core_mthd_dac },
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{ "SOR", 2, &nv50_disp_core_mthd_sor },
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{ "PIOR", 3, &nv50_disp_core_mthd_pior },
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{ "HEAD", 2, &g84_disp_core_mthd_head },
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{}
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}
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};
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/*******************************************************************************
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* EVO sync channel objects
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******************************************************************************/
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static const struct nv50_disp_mthd_list
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g84_disp_base_mthd_base = {
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.mthd = 0x0000,
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.addr = 0x000000,
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.data = {
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{ 0x0080, 0x000000 },
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{ 0x0084, 0x0008c4 },
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{ 0x0088, 0x0008d0 },
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{ 0x008c, 0x0008dc },
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{ 0x0090, 0x0008e4 },
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{ 0x0094, 0x610884 },
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{ 0x00a0, 0x6108a0 },
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{ 0x00a4, 0x610878 },
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{ 0x00c0, 0x61086c },
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{ 0x00c4, 0x610800 },
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{ 0x00c8, 0x61080c },
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{ 0x00cc, 0x610818 },
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{ 0x00e0, 0x610858 },
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{ 0x00e4, 0x610860 },
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{ 0x00e8, 0x6108ac },
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{ 0x00ec, 0x6108b4 },
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{ 0x00fc, 0x610824 },
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{ 0x0100, 0x610894 },
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{ 0x0104, 0x61082c },
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{ 0x0110, 0x6108bc },
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{ 0x0114, 0x61088c },
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{}
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}
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};
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const struct nv50_disp_mthd_chan
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g84_disp_base_mthd_chan = {
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.name = "Base",
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.addr = 0x000540,
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.data = {
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{ "Global", 1, &g84_disp_base_mthd_base },
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{ "Image", 2, &nv50_disp_base_mthd_image },
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{}
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}
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};
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/*******************************************************************************
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* EVO overlay channel objects
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******************************************************************************/
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static const struct nv50_disp_mthd_list
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g84_disp_ovly_mthd_base = {
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.mthd = 0x0000,
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.addr = 0x000000,
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.data = {
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{ 0x0080, 0x000000 },
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{ 0x0084, 0x6109a0 },
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{ 0x0088, 0x6109c0 },
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{ 0x008c, 0x6109c8 },
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{ 0x0090, 0x6109b4 },
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{ 0x0094, 0x610970 },
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{ 0x00a0, 0x610998 },
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{ 0x00a4, 0x610964 },
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{ 0x00c0, 0x610958 },
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{ 0x00e0, 0x6109a8 },
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{ 0x00e4, 0x6109d0 },
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{ 0x00e8, 0x6109d8 },
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{ 0x0100, 0x61094c },
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{ 0x0104, 0x610984 },
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{ 0x0108, 0x61098c },
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{ 0x0800, 0x6109f8 },
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{ 0x0808, 0x610a08 },
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{ 0x080c, 0x610a10 },
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{ 0x0810, 0x610a00 },
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{}
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}
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};
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const struct nv50_disp_mthd_chan
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g84_disp_ovly_mthd_chan = {
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.name = "Overlay",
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.addr = 0x000540,
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.data = {
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{ "Global", 1, &g84_disp_ovly_mthd_base },
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{}
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}
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};
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/*******************************************************************************
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* Base display object
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******************************************************************************/
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static struct nvkm_oclass
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g84_disp_sclass[] = {
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{ G82_DISP_CORE_CHANNEL_DMA, &nv50_disp_core_ofuncs.base },
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{ G82_DISP_BASE_CHANNEL_DMA, &nv50_disp_base_ofuncs.base },
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{ G82_DISP_OVERLAY_CHANNEL_DMA, &nv50_disp_ovly_ofuncs.base },
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{ G82_DISP_OVERLAY, &nv50_disp_oimm_ofuncs.base },
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{ G82_DISP_CURSOR, &nv50_disp_curs_ofuncs.base },
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{}
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};
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static struct nvkm_oclass
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g84_disp_main_oclass[] = {
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{ G82_DISP, &nv50_disp_main_ofuncs },
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{}
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};
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/*******************************************************************************
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* Display engine implementation
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******************************************************************************/
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static int
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g84_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
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struct nvkm_oclass *oclass, void *data, u32 size,
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struct nvkm_object **pobject)
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{
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struct nv50_disp_priv *priv;
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int ret;
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ret = nvkm_disp_create(parent, engine, oclass, 2, "PDISP",
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"display", &priv);
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*pobject = nv_object(priv);
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if (ret)
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return ret;
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ret = nvkm_event_init(&nv50_disp_chan_uevent, 1, 9, &priv->uevent);
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if (ret)
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return ret;
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nv_engine(priv)->sclass = g84_disp_main_oclass;
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nv_engine(priv)->cclass = &nv50_disp_cclass;
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nv_subdev(priv)->intr = nv50_disp_intr;
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INIT_WORK(&priv->supervisor, nv50_disp_intr_supervisor);
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priv->sclass = g84_disp_sclass;
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priv->head.nr = 2;
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priv->dac.nr = 3;
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priv->sor.nr = 2;
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priv->pior.nr = 3;
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priv->dac.power = nv50_dac_power;
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priv->dac.sense = nv50_dac_sense;
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priv->sor.power = nv50_sor_power;
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priv->sor.hdmi = g84_hdmi_ctrl;
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priv->pior.power = nv50_pior_power;
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return 0;
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}
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struct nvkm_oclass *
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g84_disp_oclass = &(struct nv50_disp_impl) {
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.base.base.handle = NV_ENGINE(DISP, 0x82),
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.base.base.ofuncs = &(struct nvkm_ofuncs) {
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.ctor = g84_disp_ctor,
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.dtor = _nvkm_disp_dtor,
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.init = _nvkm_disp_init,
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.fini = _nvkm_disp_fini,
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},
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.base.vblank = &nv50_disp_vblank_func,
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.base.outp = nv50_disp_outp_sclass,
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.mthd.core = &g84_disp_core_mthd_chan,
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.mthd.base = &g84_disp_base_mthd_chan,
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.mthd.ovly = &g84_disp_ovly_mthd_chan,
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.mthd.prev = 0x000004,
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.head.scanoutpos = nv50_disp_main_scanoutpos,
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}.base.base;
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