bd6c5cab95
The namespace of NVKM is being changed to nvkm_ instead of nouveau_, which will be used for the DRM part of the driver. This is being done in order to make it very clear as to what part of the driver a given symbol belongs to, and as a minor step towards splitting the DRM driver out to be able to stand on its own (for virt). Because there's already a large amount of churn here anyway, this is as good a time as any to also switch to NVIDIA's device and chipset naming to ease collaboration with them. A comparison of objdump disassemblies proves no code changes. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
166 lines
4.7 KiB
C
166 lines
4.7 KiB
C
/*
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* Copyright 2012 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include <engine/ce.h>
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#include <engine/falcon.h>
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#include "fuc/gf100.fuc3.h"
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struct gf100_ce_priv {
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struct nvkm_falcon base;
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};
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/*******************************************************************************
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* Copy object classes
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******************************************************************************/
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static struct nvkm_oclass
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gf100_ce0_sclass[] = {
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{ 0x90b5, &nvkm_object_ofuncs },
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{},
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};
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static struct nvkm_oclass
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gf100_ce1_sclass[] = {
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{ 0x90b8, &nvkm_object_ofuncs },
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{},
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};
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/*******************************************************************************
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* PCE context
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******************************************************************************/
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static struct nvkm_ofuncs
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gf100_ce_context_ofuncs = {
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.ctor = _nvkm_falcon_context_ctor,
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.dtor = _nvkm_falcon_context_dtor,
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.init = _nvkm_falcon_context_init,
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.fini = _nvkm_falcon_context_fini,
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.rd32 = _nvkm_falcon_context_rd32,
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.wr32 = _nvkm_falcon_context_wr32,
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};
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static struct nvkm_oclass
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gf100_ce0_cclass = {
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.handle = NV_ENGCTX(CE0, 0xc0),
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.ofuncs = &gf100_ce_context_ofuncs,
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};
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static struct nvkm_oclass
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gf100_ce1_cclass = {
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.handle = NV_ENGCTX(CE1, 0xc0),
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.ofuncs = &gf100_ce_context_ofuncs,
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};
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/*******************************************************************************
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* PCE engine/subdev functions
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******************************************************************************/
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static int
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gf100_ce_init(struct nvkm_object *object)
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{
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struct gf100_ce_priv *priv = (void *)object;
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int ret;
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ret = nvkm_falcon_init(&priv->base);
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if (ret)
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return ret;
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nv_wo32(priv, 0x084, nv_engidx(&priv->base.base) - NVDEV_ENGINE_CE0);
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return 0;
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}
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static int
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gf100_ce0_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
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struct nvkm_oclass *oclass, void *data, u32 size,
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struct nvkm_object **pobject)
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{
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struct gf100_ce_priv *priv;
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int ret;
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ret = nvkm_falcon_create(parent, engine, oclass, 0x104000, true,
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"PCE0", "ce0", &priv);
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*pobject = nv_object(priv);
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if (ret)
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return ret;
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nv_subdev(priv)->unit = 0x00000040;
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nv_subdev(priv)->intr = gt215_ce_intr;
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nv_engine(priv)->cclass = &gf100_ce0_cclass;
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nv_engine(priv)->sclass = gf100_ce0_sclass;
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nv_falcon(priv)->code.data = gf100_pce_code;
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nv_falcon(priv)->code.size = sizeof(gf100_pce_code);
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nv_falcon(priv)->data.data = gf100_pce_data;
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nv_falcon(priv)->data.size = sizeof(gf100_pce_data);
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return 0;
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}
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static int
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gf100_ce1_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
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struct nvkm_oclass *oclass, void *data, u32 size,
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struct nvkm_object **pobject)
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{
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struct gf100_ce_priv *priv;
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int ret;
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ret = nvkm_falcon_create(parent, engine, oclass, 0x105000, true,
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"PCE1", "ce1", &priv);
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*pobject = nv_object(priv);
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if (ret)
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return ret;
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nv_subdev(priv)->unit = 0x00000080;
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nv_subdev(priv)->intr = gt215_ce_intr;
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nv_engine(priv)->cclass = &gf100_ce1_cclass;
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nv_engine(priv)->sclass = gf100_ce1_sclass;
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nv_falcon(priv)->code.data = gf100_pce_code;
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nv_falcon(priv)->code.size = sizeof(gf100_pce_code);
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nv_falcon(priv)->data.data = gf100_pce_data;
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nv_falcon(priv)->data.size = sizeof(gf100_pce_data);
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return 0;
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}
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struct nvkm_oclass
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gf100_ce0_oclass = {
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.handle = NV_ENGINE(CE0, 0xc0),
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.ofuncs = &(struct nvkm_ofuncs) {
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.ctor = gf100_ce0_ctor,
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.dtor = _nvkm_falcon_dtor,
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.init = gf100_ce_init,
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.fini = _nvkm_falcon_fini,
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.rd32 = _nvkm_falcon_rd32,
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.wr32 = _nvkm_falcon_wr32,
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},
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};
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struct nvkm_oclass
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gf100_ce1_oclass = {
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.handle = NV_ENGINE(CE1, 0xc0),
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.ofuncs = &(struct nvkm_ofuncs) {
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.ctor = gf100_ce1_ctor,
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.dtor = _nvkm_falcon_dtor,
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.init = gf100_ce_init,
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.fini = _nvkm_falcon_fini,
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.rd32 = _nvkm_falcon_rd32,
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.wr32 = _nvkm_falcon_wr32,
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},
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};
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