c1a2562ac5
This implements support for MSIs on p5ioc2 PHBs. We only support MSIs on the PCIe PHBs, not the PCI-X ones as the later hasn't been properly verified in HW. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
234 lines
6.5 KiB
C
234 lines
6.5 KiB
C
/*
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* Support PCI/PCIe on PowerNV platforms
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*
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* Currently supports only P5IOC2
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*
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* Copyright 2011 Benjamin Herrenschmidt, IBM Corp.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/delay.h>
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#include <linux/string.h>
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#include <linux/init.h>
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#include <linux/bootmem.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <linux/msi.h>
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#include <asm/sections.h>
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#include <asm/io.h>
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#include <asm/prom.h>
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#include <asm/pci-bridge.h>
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#include <asm/machdep.h>
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#include <asm/ppc-pci.h>
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#include <asm/opal.h>
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#include <asm/iommu.h>
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#include <asm/tce.h>
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#include <asm/abs_addr.h>
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#include "powernv.h"
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#include "pci.h"
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/* For now, use a fixed amount of TCE memory for each p5ioc2
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* hub, 16M will do
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*/
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#define P5IOC2_TCE_MEMORY 0x01000000
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#ifdef CONFIG_PCI_MSI
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static int pnv_pci_p5ioc2_msi_setup(struct pnv_phb *phb, struct pci_dev *dev,
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unsigned int hwirq, unsigned int is_64,
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struct msi_msg *msg)
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{
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if (WARN_ON(!is_64))
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return -ENXIO;
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msg->data = hwirq - phb->msi_base;
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msg->address_hi = 0x10000000;
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msg->address_lo = 0;
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return 0;
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}
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static void pnv_pci_init_p5ioc2_msis(struct pnv_phb *phb)
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{
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unsigned int bmap_size;
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const __be32 *prop = of_get_property(phb->hose->dn,
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"ibm,opal-msi-ranges", NULL);
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if (!prop)
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return;
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/* Don't do MSI's on p5ioc2 PCI-X are they are not properly
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* verified in HW
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*/
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if (of_device_is_compatible(phb->hose->dn, "ibm,p5ioc2-pcix"))
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return;
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phb->msi_base = be32_to_cpup(prop);
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phb->msi_count = be32_to_cpup(prop + 1);
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bmap_size = BITS_TO_LONGS(phb->msi_count) * sizeof(unsigned long);
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phb->msi_map = zalloc_maybe_bootmem(bmap_size, GFP_KERNEL);
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if (!phb->msi_map) {
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pr_err("PCI %d: Failed to allocate MSI bitmap !\n",
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phb->hose->global_number);
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return;
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}
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phb->msi_setup = pnv_pci_p5ioc2_msi_setup;
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phb->msi32_support = 0;
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pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n",
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phb->msi_count, phb->msi_base);
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}
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#else
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static void pnv_pci_init_p5ioc2_msis(struct pnv_phb *phb) { }
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#endif /* CONFIG_PCI_MSI */
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static void __devinit pnv_pci_p5ioc2_dma_dev_setup(struct pnv_phb *phb,
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struct pci_dev *pdev)
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{
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if (phb->p5ioc2.iommu_table.it_map == NULL)
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iommu_init_table(&phb->p5ioc2.iommu_table, phb->hose->node);
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set_iommu_table_base(&pdev->dev, &phb->p5ioc2.iommu_table);
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}
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static void __init pnv_pci_init_p5ioc2_phb(struct device_node *np,
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void *tce_mem, u64 tce_size)
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{
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struct pnv_phb *phb;
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const u64 *prop64;
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u64 phb_id;
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int64_t rc;
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static int primary = 1;
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pr_info(" Initializing p5ioc2 PHB %s\n", np->full_name);
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prop64 = of_get_property(np, "ibm,opal-phbid", NULL);
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if (!prop64) {
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pr_err(" Missing \"ibm,opal-phbid\" property !\n");
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return;
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}
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phb_id = be64_to_cpup(prop64);
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pr_devel(" PHB-ID : 0x%016llx\n", phb_id);
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pr_devel(" TCE AT : 0x%016lx\n", __pa(tce_mem));
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pr_devel(" TCE SZ : 0x%016llx\n", tce_size);
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rc = opal_pci_set_phb_tce_memory(phb_id, __pa(tce_mem), tce_size);
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if (rc != OPAL_SUCCESS) {
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pr_err(" Failed to set TCE memory, OPAL error %lld\n", rc);
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return;
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}
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phb = alloc_bootmem(sizeof(struct pnv_phb));
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if (phb) {
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memset(phb, 0, sizeof(struct pnv_phb));
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phb->hose = pcibios_alloc_controller(np);
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}
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if (!phb || !phb->hose) {
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pr_err(" Failed to allocate PCI controller\n");
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return;
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}
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spin_lock_init(&phb->lock);
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phb->hose->first_busno = 0;
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phb->hose->last_busno = 0xff;
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phb->hose->private_data = phb;
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phb->opal_id = phb_id;
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phb->type = PNV_PHB_P5IOC2;
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phb->regs = of_iomap(np, 0);
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if (phb->regs == NULL)
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pr_err(" Failed to map registers !\n");
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else {
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pr_devel(" P_BUID = 0x%08x\n", in_be32(phb->regs + 0x100));
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pr_devel(" P_IOSZ = 0x%08x\n", in_be32(phb->regs + 0x1b0));
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pr_devel(" P_IO_ST = 0x%08x\n", in_be32(phb->regs + 0x1e0));
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pr_devel(" P_MEM1_H = 0x%08x\n", in_be32(phb->regs + 0x1a0));
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pr_devel(" P_MEM1_L = 0x%08x\n", in_be32(phb->regs + 0x190));
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pr_devel(" P_MSZ1_L = 0x%08x\n", in_be32(phb->regs + 0x1c0));
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pr_devel(" P_MEM_ST = 0x%08x\n", in_be32(phb->regs + 0x1d0));
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pr_devel(" P_MEM2_H = 0x%08x\n", in_be32(phb->regs + 0x2c0));
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pr_devel(" P_MEM2_L = 0x%08x\n", in_be32(phb->regs + 0x2b0));
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pr_devel(" P_MSZ2_H = 0x%08x\n", in_be32(phb->regs + 0x2d0));
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pr_devel(" P_MSZ2_L = 0x%08x\n", in_be32(phb->regs + 0x2e0));
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}
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/* Interpret the "ranges" property */
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/* This also maps the I/O region and sets isa_io/mem_base */
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pci_process_bridge_OF_ranges(phb->hose, np, primary);
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primary = 0;
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phb->hose->ops = &pnv_pci_ops;
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/* Setup MSI support */
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pnv_pci_init_p5ioc2_msis(phb);
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/* Setup TCEs */
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phb->dma_dev_setup = pnv_pci_p5ioc2_dma_dev_setup;
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pnv_pci_setup_iommu_table(&phb->p5ioc2.iommu_table,
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tce_mem, tce_size, 0);
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}
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void __init pnv_pci_init_p5ioc2_hub(struct device_node *np)
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{
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struct device_node *phbn;
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const u64 *prop64;
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u64 hub_id;
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void *tce_mem;
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uint64_t tce_per_phb;
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int64_t rc;
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int phb_count = 0;
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pr_info("Probing p5ioc2 IO-Hub %s\n", np->full_name);
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prop64 = of_get_property(np, "ibm,opal-hubid", NULL);
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if (!prop64) {
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pr_err(" Missing \"ibm,opal-hubid\" property !\n");
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return;
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}
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hub_id = be64_to_cpup(prop64);
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pr_info(" HUB-ID : 0x%016llx\n", hub_id);
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/* Currently allocate 16M of TCE memory for every Hub
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*
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* XXX TODO: Make it chip local if possible
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*/
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tce_mem = __alloc_bootmem(P5IOC2_TCE_MEMORY, P5IOC2_TCE_MEMORY,
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__pa(MAX_DMA_ADDRESS));
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if (!tce_mem) {
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pr_err(" Failed to allocate TCE Memory !\n");
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return;
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}
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pr_debug(" TCE : 0x%016lx..0x%016lx\n",
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__pa(tce_mem), __pa(tce_mem) + P5IOC2_TCE_MEMORY - 1);
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rc = opal_pci_set_hub_tce_memory(hub_id, __pa(tce_mem),
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P5IOC2_TCE_MEMORY);
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if (rc != OPAL_SUCCESS) {
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pr_err(" Failed to allocate TCE memory, OPAL error %lld\n", rc);
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return;
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}
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/* Count child PHBs */
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for_each_child_of_node(np, phbn) {
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if (of_device_is_compatible(phbn, "ibm,p5ioc2-pcix") ||
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of_device_is_compatible(phbn, "ibm,p5ioc2-pciex"))
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phb_count++;
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}
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/* Calculate how much TCE space we can give per PHB */
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tce_per_phb = __rounddown_pow_of_two(P5IOC2_TCE_MEMORY / phb_count);
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pr_info(" Allocating %lld MB of TCE memory per PHB\n",
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tce_per_phb >> 20);
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/* Initialize PHBs */
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for_each_child_of_node(np, phbn) {
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if (of_device_is_compatible(phbn, "ibm,p5ioc2-pcix") ||
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of_device_is_compatible(phbn, "ibm,p5ioc2-pciex")) {
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pnv_pci_init_p5ioc2_phb(phbn, tce_mem, tce_per_phb);
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tce_mem += tce_per_phb;
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}
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}
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}
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