452976b298
The read[bwl] and write[bwl] functions are meant for accessing PCI devices. How this is achieved on AVR32 is unknown, as there are no systems with a PCI bridge available yet. On-chip peripheral access, however, should not depend on how we end up implementing PCI access, so using __raw_read[bwl]/__raw_write[bwl] is the right thing to do for on-chip peripherals. This patch converts the drivers for the static memory controller, interrupt controller, PIO controller and system manager to use __raw MMIO access. Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
127 lines
3.7 KiB
C
127 lines
3.7 KiB
C
/*
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* Register definitions for Atmel Static Memory Controller (SMC)
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*
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* Copyright (C) 2006 Atmel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_AVR32_HSMC_H__
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#define __ASM_AVR32_HSMC_H__
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/* HSMC register offsets */
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#define HSMC_SETUP0 0x0000
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#define HSMC_PULSE0 0x0004
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#define HSMC_CYCLE0 0x0008
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#define HSMC_MODE0 0x000c
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#define HSMC_SETUP1 0x0010
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#define HSMC_PULSE1 0x0014
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#define HSMC_CYCLE1 0x0018
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#define HSMC_MODE1 0x001c
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#define HSMC_SETUP2 0x0020
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#define HSMC_PULSE2 0x0024
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#define HSMC_CYCLE2 0x0028
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#define HSMC_MODE2 0x002c
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#define HSMC_SETUP3 0x0030
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#define HSMC_PULSE3 0x0034
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#define HSMC_CYCLE3 0x0038
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#define HSMC_MODE3 0x003c
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#define HSMC_SETUP4 0x0040
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#define HSMC_PULSE4 0x0044
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#define HSMC_CYCLE4 0x0048
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#define HSMC_MODE4 0x004c
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#define HSMC_SETUP5 0x0050
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#define HSMC_PULSE5 0x0054
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#define HSMC_CYCLE5 0x0058
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#define HSMC_MODE5 0x005c
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/* Bitfields in SETUP0 */
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#define HSMC_NWE_SETUP_OFFSET 0
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#define HSMC_NWE_SETUP_SIZE 6
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#define HSMC_NCS_WR_SETUP_OFFSET 8
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#define HSMC_NCS_WR_SETUP_SIZE 6
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#define HSMC_NRD_SETUP_OFFSET 16
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#define HSMC_NRD_SETUP_SIZE 6
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#define HSMC_NCS_RD_SETUP_OFFSET 24
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#define HSMC_NCS_RD_SETUP_SIZE 6
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/* Bitfields in PULSE0 */
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#define HSMC_NWE_PULSE_OFFSET 0
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#define HSMC_NWE_PULSE_SIZE 7
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#define HSMC_NCS_WR_PULSE_OFFSET 8
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#define HSMC_NCS_WR_PULSE_SIZE 7
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#define HSMC_NRD_PULSE_OFFSET 16
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#define HSMC_NRD_PULSE_SIZE 7
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#define HSMC_NCS_RD_PULSE_OFFSET 24
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#define HSMC_NCS_RD_PULSE_SIZE 7
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/* Bitfields in CYCLE0 */
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#define HSMC_NWE_CYCLE_OFFSET 0
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#define HSMC_NWE_CYCLE_SIZE 9
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#define HSMC_NRD_CYCLE_OFFSET 16
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#define HSMC_NRD_CYCLE_SIZE 9
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/* Bitfields in MODE0 */
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#define HSMC_READ_MODE_OFFSET 0
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#define HSMC_READ_MODE_SIZE 1
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#define HSMC_WRITE_MODE_OFFSET 1
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#define HSMC_WRITE_MODE_SIZE 1
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#define HSMC_EXNW_MODE_OFFSET 4
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#define HSMC_EXNW_MODE_SIZE 2
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#define HSMC_BAT_OFFSET 8
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#define HSMC_BAT_SIZE 1
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#define HSMC_DBW_OFFSET 12
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#define HSMC_DBW_SIZE 2
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#define HSMC_TDF_CYCLES_OFFSET 16
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#define HSMC_TDF_CYCLES_SIZE 4
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#define HSMC_TDF_MODE_OFFSET 20
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#define HSMC_TDF_MODE_SIZE 1
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#define HSMC_PMEN_OFFSET 24
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#define HSMC_PMEN_SIZE 1
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#define HSMC_PS_OFFSET 28
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#define HSMC_PS_SIZE 2
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/* Constants for READ_MODE */
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#define HSMC_READ_MODE_NCS_CONTROLLED 0
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#define HSMC_READ_MODE_NRD_CONTROLLED 1
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/* Constants for WRITE_MODE */
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#define HSMC_WRITE_MODE_NCS_CONTROLLED 0
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#define HSMC_WRITE_MODE_NWE_CONTROLLED 1
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/* Constants for EXNW_MODE */
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#define HSMC_EXNW_MODE_DISABLED 0
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#define HSMC_EXNW_MODE_RESERVED 1
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#define HSMC_EXNW_MODE_FROZEN 2
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#define HSMC_EXNW_MODE_READY 3
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/* Constants for BAT */
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#define HSMC_BAT_BYTE_SELECT 0
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#define HSMC_BAT_BYTE_WRITE 1
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/* Constants for DBW */
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#define HSMC_DBW_8_BITS 0
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#define HSMC_DBW_16_BITS 1
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#define HSMC_DBW_32_BITS 2
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/* Bit manipulation macros */
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#define HSMC_BIT(name) \
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(1 << HSMC_##name##_OFFSET)
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#define HSMC_BF(name,value) \
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(((value) & ((1 << HSMC_##name##_SIZE) - 1)) \
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<< HSMC_##name##_OFFSET)
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#define HSMC_BFEXT(name,value) \
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(((value) >> HSMC_##name##_OFFSET) \
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& ((1 << HSMC_##name##_SIZE) - 1))
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#define HSMC_BFINS(name,value,old) \
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(((old) & ~(((1 << HSMC_##name##_SIZE) - 1) \
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<< HSMC_##name##_OFFSET)) | HSMC_BF(name,value))
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/* Register access macros */
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#define hsmc_readl(port,reg) \
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__raw_readl((port)->regs + HSMC_##reg)
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#define hsmc_writel(port,reg,value) \
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__raw_writel((value), (port)->regs + HSMC_##reg)
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#endif /* __ASM_AVR32_HSMC_H__ */
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