 25985edced
			
		
	
	
	25985edced
	
	
	
		
			
			Fixes generated by 'codespell' and manually reviewed. Signed-off-by: Lucas De Marchi <lucas.demarchi@profusion.mobi>
		
			
				
	
	
		
			370 lines
		
	
	
	
		
			20 KiB
			
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			370 lines
		
	
	
	
		
			20 KiB
			
		
	
	
	
		
			C
		
	
	
	
	
	
| /*
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|  * Copyright (C) 2009 Nokia
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|  * Copyright (C) 2009 Texas Instruments
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|  *
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|  * This program is free software; you can redistribute it and/or modify
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|  * it under the terms of the GNU General Public License version 2 as
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|  * published by the Free Software Foundation.
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|  */
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| 
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| #define OMAP2430_CONTROL_PADCONF_MUX_PBASE			0x49002030LU
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| 
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| #define OMAP2430_MUX(mode0, mux_value)					\
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| {									\
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| 	.reg_offset	= (OMAP2430_CONTROL_PADCONF_##mode0##_OFFSET),	\
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| 	.value		= (mux_value),					\
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| }
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| 
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| /*
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|  * OMAP2430 CONTROL_PADCONF* register offsets for pin-muxing
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|  *
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|  * Extracted from the TRM.  Add 0x49002030 to these values to get the
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|  * absolute addresses.  The name in the macro is the mode-0 name of
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|  * the pin.  NOTE: These registers are 8-bits wide.
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|  *
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|  * Note that these defines use SDMMC instead of MMC for compatibility
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|  * with signal names used in 3630.
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|  */
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| #define OMAP2430_CONTROL_PADCONF_GPMC_CLK_OFFSET		0x000
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| #define OMAP2430_CONTROL_PADCONF_GPMC_NCS0_OFFSET		0x001
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| #define OMAP2430_CONTROL_PADCONF_GPMC_NCS1_OFFSET		0x002
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| #define OMAP2430_CONTROL_PADCONF_GPMC_NCS2_OFFSET		0x003
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| #define OMAP2430_CONTROL_PADCONF_GPMC_NCS3_OFFSET		0x004
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| #define OMAP2430_CONTROL_PADCONF_GPMC_NCS4_OFFSET		0x005
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| #define OMAP2430_CONTROL_PADCONF_GPMC_NCS5_OFFSET		0x006
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| #define OMAP2430_CONTROL_PADCONF_GPMC_NCS6_OFFSET		0x007
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| #define OMAP2430_CONTROL_PADCONF_GPMC_NCS7_OFFSET		0x008
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| #define OMAP2430_CONTROL_PADCONF_GPMC_NADV_ALE_OFFSET		0x009
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| #define OMAP2430_CONTROL_PADCONF_GPMC_NOE_NRE_OFFSET		0x00a
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| #define OMAP2430_CONTROL_PADCONF_GPMC_NWE_OFFSET		0x00b
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| #define OMAP2430_CONTROL_PADCONF_GPMC_NBE0_CLE_OFFSET		0x00c
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| #define OMAP2430_CONTROL_PADCONF_GPMC_NBE1_OFFSET		0x00d
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| #define OMAP2430_CONTROL_PADCONF_GPMC_NWP_OFFSET		0x00e
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| #define OMAP2430_CONTROL_PADCONF_GPMC_WAIT0_OFFSET		0x00f
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| #define OMAP2430_CONTROL_PADCONF_GPMC_WAIT1_OFFSET		0x010
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| #define OMAP2430_CONTROL_PADCONF_GPMC_WAIT2_OFFSET		0x011
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| #define OMAP2430_CONTROL_PADCONF_GPMC_WAIT3_OFFSET		0x012
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| #define OMAP2430_CONTROL_PADCONF_SDRC_CLK_OFFSET		0x013
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| #define OMAP2430_CONTROL_PADCONF_SDRC_NCLK_OFFSET		0x014
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| #define OMAP2430_CONTROL_PADCONF_SDRC_NCS0_OFFSET		0x015
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| #define OMAP2430_CONTROL_PADCONF_SDRC_NCS1_OFFSET		0x016
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| #define OMAP2430_CONTROL_PADCONF_SDRC_CKE0_OFFSET		0x017
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| #define OMAP2430_CONTROL_PADCONF_SDRC_CKE1_OFFSET		0x018
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| #define OMAP2430_CONTROL_PADCONF_SDRC_NRAS_OFFSET		0x019
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| #define OMAP2430_CONTROL_PADCONF_SDRC_NCAS_OFFSET		0x01a
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| #define OMAP2430_CONTROL_PADCONF_SDRC_NWE_OFFSET		0x01b
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| #define OMAP2430_CONTROL_PADCONF_SDRC_DM0_OFFSET		0x01c
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| #define OMAP2430_CONTROL_PADCONF_SDRC_DM1_OFFSET		0x01d
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| #define OMAP2430_CONTROL_PADCONF_SDRC_DM2_OFFSET		0x01e
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| #define OMAP2430_CONTROL_PADCONF_SDRC_DM3_OFFSET		0x01f
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| #define OMAP2430_CONTROL_PADCONF_SDRC_DQS0_OFFSET		0x020
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| #define OMAP2430_CONTROL_PADCONF_SDRC_DQS1_OFFSET		0x021
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| #define OMAP2430_CONTROL_PADCONF_SDRC_DQS2_OFFSET		0x022
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| #define OMAP2430_CONTROL_PADCONF_SDRC_DQS3_OFFSET		0x023
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| #define OMAP2430_CONTROL_PADCONF_SDRC_A14_OFFSET		0x024
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| #define OMAP2430_CONTROL_PADCONF_SDRC_A13_OFFSET		0x025
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| #define OMAP2430_CONTROL_PADCONF_SDRC_A12_OFFSET		0x026
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| #define OMAP2430_CONTROL_PADCONF_SDRC_BA1_OFFSET		0x027
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| #define OMAP2430_CONTROL_PADCONF_SDRC_BA0_OFFSET		0x028
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| #define OMAP2430_CONTROL_PADCONF_SDRC_A11_OFFSET		0x029
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| #define OMAP2430_CONTROL_PADCONF_SDRC_A10_OFFSET		0x02a
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| #define OMAP2430_CONTROL_PADCONF_SDRC_A9_OFFSET			0x02b
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| #define OMAP2430_CONTROL_PADCONF_SDRC_A8_OFFSET			0x02c
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| #define OMAP2430_CONTROL_PADCONF_SDRC_A7_OFFSET			0x02d
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| #define OMAP2430_CONTROL_PADCONF_SDRC_A6_OFFSET			0x02e
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| #define OMAP2430_CONTROL_PADCONF_SDRC_A5_OFFSET			0x02f
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| #define OMAP2430_CONTROL_PADCONF_SDRC_A4_OFFSET			0x030
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| #define OMAP2430_CONTROL_PADCONF_SDRC_A3_OFFSET			0x031
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| #define OMAP2430_CONTROL_PADCONF_SDRC_A2_OFFSET			0x032
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| #define OMAP2430_CONTROL_PADCONF_SDRC_A1_OFFSET			0x033
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| #define OMAP2430_CONTROL_PADCONF_SDRC_A0_OFFSET			0x034
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| #define OMAP2430_CONTROL_PADCONF_SDRC_D31_OFFSET		0x035
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| #define OMAP2430_CONTROL_PADCONF_SDRC_D30_OFFSET		0x036
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| #define OMAP2430_CONTROL_PADCONF_SDRC_D29_OFFSET		0x037
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| #define OMAP2430_CONTROL_PADCONF_SDRC_D28_OFFSET		0x038
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| #define OMAP2430_CONTROL_PADCONF_SDRC_D27_OFFSET		0x039
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| #define OMAP2430_CONTROL_PADCONF_SDRC_D26_OFFSET		0x03a
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| #define OMAP2430_CONTROL_PADCONF_SDRC_D25_OFFSET		0x03b
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| #define OMAP2430_CONTROL_PADCONF_SDRC_D24_OFFSET		0x03c
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| #define OMAP2430_CONTROL_PADCONF_SDRC_D23_OFFSET		0x03d
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| #define OMAP2430_CONTROL_PADCONF_SDRC_D22_OFFSET		0x03e
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| #define OMAP2430_CONTROL_PADCONF_SDRC_D21_OFFSET		0x03f
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| #define OMAP2430_CONTROL_PADCONF_SDRC_D20_OFFSET		0x040
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| #define OMAP2430_CONTROL_PADCONF_SDRC_D19_OFFSET		0x041
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| #define OMAP2430_CONTROL_PADCONF_SDRC_D18_OFFSET		0x042
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| #define OMAP2430_CONTROL_PADCONF_SDRC_D17_OFFSET		0x043
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| #define OMAP2430_CONTROL_PADCONF_SDRC_D16_OFFSET		0x044
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| #define OMAP2430_CONTROL_PADCONF_SDRC_D15_OFFSET		0x045
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| #define OMAP2430_CONTROL_PADCONF_SDRC_D14_OFFSET		0x046
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| #define OMAP2430_CONTROL_PADCONF_SDRC_D13_OFFSET		0x047
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| #define OMAP2430_CONTROL_PADCONF_SDRC_D12_OFFSET		0x048
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| #define OMAP2430_CONTROL_PADCONF_SDRC_D11_OFFSET		0x049
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| #define OMAP2430_CONTROL_PADCONF_SDRC_D10_OFFSET		0x04a
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| #define OMAP2430_CONTROL_PADCONF_SDRC_D9_OFFSET			0x04b
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| #define OMAP2430_CONTROL_PADCONF_SDRC_D8_OFFSET			0x04c
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| #define OMAP2430_CONTROL_PADCONF_SDRC_D7_OFFSET			0x04d
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| #define OMAP2430_CONTROL_PADCONF_SDRC_D6_OFFSET			0x04e
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| #define OMAP2430_CONTROL_PADCONF_SDRC_D5_OFFSET			0x04f
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| #define OMAP2430_CONTROL_PADCONF_SDRC_D4_OFFSET			0x050
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| #define OMAP2430_CONTROL_PADCONF_SDRC_D3_OFFSET			0x051
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| #define OMAP2430_CONTROL_PADCONF_SDRC_D2_OFFSET			0x052
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| #define OMAP2430_CONTROL_PADCONF_SDRC_D1_OFFSET			0x053
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| #define OMAP2430_CONTROL_PADCONF_SDRC_D0_OFFSET			0x054
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| #define OMAP2430_CONTROL_PADCONF_GPMC_A10_OFFSET		0x055
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| #define OMAP2430_CONTROL_PADCONF_GPMC_A9_OFFSET			0x056
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| #define OMAP2430_CONTROL_PADCONF_GPMC_A8_OFFSET			0x057
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| #define OMAP2430_CONTROL_PADCONF_GPMC_A7_OFFSET			0x058
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| #define OMAP2430_CONTROL_PADCONF_GPMC_A6_OFFSET			0x059
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| #define OMAP2430_CONTROL_PADCONF_GPMC_A5_OFFSET			0x05a
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| #define OMAP2430_CONTROL_PADCONF_GPMC_A4_OFFSET			0x05b
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| #define OMAP2430_CONTROL_PADCONF_GPMC_A3_OFFSET			0x05c
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| #define OMAP2430_CONTROL_PADCONF_GPMC_A2_OFFSET			0x05d
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| #define OMAP2430_CONTROL_PADCONF_GPMC_A1_OFFSET			0x05e
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| #define OMAP2430_CONTROL_PADCONF_GPMC_D15_OFFSET		0x05f
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| #define OMAP2430_CONTROL_PADCONF_GPMC_D14_OFFSET		0x060
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| #define OMAP2430_CONTROL_PADCONF_GPMC_D13_OFFSET		0x061
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| #define OMAP2430_CONTROL_PADCONF_GPMC_D12_OFFSET		0x062
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| #define OMAP2430_CONTROL_PADCONF_GPMC_D11_OFFSET		0x063
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| #define OMAP2430_CONTROL_PADCONF_GPMC_D10_OFFSET		0x064
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| #define OMAP2430_CONTROL_PADCONF_GPMC_D9_OFFSET			0x065
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| #define OMAP2430_CONTROL_PADCONF_GPMC_D8_OFFSET			0x066
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| #define OMAP2430_CONTROL_PADCONF_GPMC_D7_OFFSET			0x067
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| #define OMAP2430_CONTROL_PADCONF_GPMC_D6_OFFSET			0x068
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| #define OMAP2430_CONTROL_PADCONF_GPMC_D5_OFFSET			0x069
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| #define OMAP2430_CONTROL_PADCONF_GPMC_D4_OFFSET			0x06a
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| #define OMAP2430_CONTROL_PADCONF_GPMC_D3_OFFSET			0x06b
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| #define OMAP2430_CONTROL_PADCONF_GPMC_D2_OFFSET			0x06c
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| #define OMAP2430_CONTROL_PADCONF_GPMC_D1_OFFSET			0x06d
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| #define OMAP2430_CONTROL_PADCONF_GPMC_D0_OFFSET			0x06e
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| #define OMAP2430_CONTROL_PADCONF_DSS_DATA0_OFFSET		0x06f
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| #define OMAP2430_CONTROL_PADCONF_DSS_DATA1_OFFSET		0x070
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| #define OMAP2430_CONTROL_PADCONF_DSS_DATA2_OFFSET		0x071
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| #define OMAP2430_CONTROL_PADCONF_DSS_DATA3_OFFSET		0x072
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| #define OMAP2430_CONTROL_PADCONF_DSS_DATA4_OFFSET		0x073
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| #define OMAP2430_CONTROL_PADCONF_DSS_DATA5_OFFSET		0x074
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| #define OMAP2430_CONTROL_PADCONF_DSS_DATA6_OFFSET		0x075
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| #define OMAP2430_CONTROL_PADCONF_DSS_DATA7_OFFSET		0x076
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| #define OMAP2430_CONTROL_PADCONF_DSS_DATA8_OFFSET		0x077
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| #define OMAP2430_CONTROL_PADCONF_DSS_DATA9_OFFSET		0x078
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| #define OMAP2430_CONTROL_PADCONF_DSS_DATA10_OFFSET		0x079
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| #define OMAP2430_CONTROL_PADCONF_DSS_DATA11_OFFSET		0x07a
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| #define OMAP2430_CONTROL_PADCONF_DSS_DATA12_OFFSET		0x07b
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| #define OMAP2430_CONTROL_PADCONF_DSS_DATA13_OFFSET		0x07c
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| #define OMAP2430_CONTROL_PADCONF_DSS_DATA14_OFFSET		0x07d
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| #define OMAP2430_CONTROL_PADCONF_DSS_DATA15_OFFSET		0x07e
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| #define OMAP2430_CONTROL_PADCONF_DSS_DATA16_OFFSET		0x07f
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| #define OMAP2430_CONTROL_PADCONF_DSS_DATA17_OFFSET		0x080
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| #define OMAP2430_CONTROL_PADCONF_UART1_CTS_OFFSET		0x081
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| #define OMAP2430_CONTROL_PADCONF_UART1_RTS_OFFSET		0x082
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| #define OMAP2430_CONTROL_PADCONF_UART1_TX_OFFSET		0x083
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| #define OMAP2430_CONTROL_PADCONF_UART1_RX_OFFSET		0x084
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| #define OMAP2430_CONTROL_PADCONF_MCBSP2_DR_OFFSET		0x085
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| #define OMAP2430_CONTROL_PADCONF_MCBSP2_CLKX_OFFSET		0x086
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| #define OMAP2430_CONTROL_PADCONF_DSS_PCLK_OFFSET		0x087
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| #define OMAP2430_CONTROL_PADCONF_DSS_VSYNC_OFFSET		0x088
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| #define OMAP2430_CONTROL_PADCONF_DSS_HSYNC_OFFSET		0x089
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| #define OMAP2430_CONTROL_PADCONF_DSS_ACBIAS_OFFSET		0x08a
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| #define OMAP2430_CONTROL_PADCONF_SYS_NRESPWRON_OFFSET		0x08b
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| #define OMAP2430_CONTROL_PADCONF_SYS_NRESWARM_OFFSET		0x08c
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| #define OMAP2430_CONTROL_PADCONF_SYS_NIRQ0_OFFSET		0x08d
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| #define OMAP2430_CONTROL_PADCONF_SYS_NIRQ1_OFFSET		0x08e
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| #define OMAP2430_CONTROL_PADCONF_SYS_VMODE_OFFSET		0x08f
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| #define OMAP2430_CONTROL_PADCONF_GPIO_128_OFFSET		0x090
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| #define OMAP2430_CONTROL_PADCONF_GPIO_129_OFFSET		0x091
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| #define OMAP2430_CONTROL_PADCONF_GPIO_130_OFFSET		0x092
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| #define OMAP2430_CONTROL_PADCONF_GPIO_131_OFFSET		0x093
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| #define OMAP2430_CONTROL_PADCONF_SYS_32K_OFFSET			0x094
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| #define OMAP2430_CONTROL_PADCONF_SYS_XTALIN_OFFSET		0x095
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| #define OMAP2430_CONTROL_PADCONF_SYS_XTALOUT_OFFSET		0x096
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| #define OMAP2430_CONTROL_PADCONF_GPIO_132_OFFSET		0x097
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| #define OMAP2430_CONTROL_PADCONF_SYS_CLKREQ_OFFSET		0x098
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| #define OMAP2430_CONTROL_PADCONF_SYS_CLKOUT_OFFSET		0x099
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| #define OMAP2430_CONTROL_PADCONF_GPIO_151_OFFSET		0x09a
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| #define OMAP2430_CONTROL_PADCONF_GPIO_133_OFFSET		0x09b
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| #define OMAP2430_CONTROL_PADCONF_JTAG_EMU1_OFFSET		0x09c
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| #define OMAP2430_CONTROL_PADCONF_JTAG_EMU0_OFFSET		0x09d
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| #define OMAP2430_CONTROL_PADCONF_JTAG_NTRST_OFFSET		0x09e
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| #define OMAP2430_CONTROL_PADCONF_JTAG_TCK_OFFSET		0x09f
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| #define OMAP2430_CONTROL_PADCONF_JTAG_RTCK_OFFSET		0x0a0
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| #define OMAP2430_CONTROL_PADCONF_JTAG_TMS_OFFSET		0x0a1
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| #define OMAP2430_CONTROL_PADCONF_JTAG_TDI_OFFSET		0x0a2
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| #define OMAP2430_CONTROL_PADCONF_JTAG_TDO_OFFSET		0x0a3
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| #define OMAP2430_CONTROL_PADCONF_CAM_D9_OFFSET			0x0a4
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| #define OMAP2430_CONTROL_PADCONF_CAM_D8_OFFSET			0x0a5
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| #define OMAP2430_CONTROL_PADCONF_CAM_D7_OFFSET			0x0a6
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| #define OMAP2430_CONTROL_PADCONF_CAM_D6_OFFSET			0x0a7
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| #define OMAP2430_CONTROL_PADCONF_CAM_D5_OFFSET			0x0a8
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| #define OMAP2430_CONTROL_PADCONF_CAM_D4_OFFSET			0x0a9
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| #define OMAP2430_CONTROL_PADCONF_CAM_D3_OFFSET			0x0aa
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| #define OMAP2430_CONTROL_PADCONF_CAM_D2_OFFSET			0x0ab
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| #define OMAP2430_CONTROL_PADCONF_CAM_D1_OFFSET			0x0ac
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| #define OMAP2430_CONTROL_PADCONF_CAM_D0_OFFSET			0x0ad
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| #define OMAP2430_CONTROL_PADCONF_CAM_HS_OFFSET			0x0ae
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| #define OMAP2430_CONTROL_PADCONF_CAM_VS_OFFSET			0x0af
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| #define OMAP2430_CONTROL_PADCONF_CAM_LCLK_OFFSET		0x0b0
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| #define OMAP2430_CONTROL_PADCONF_CAM_XCLK_OFFSET		0x0b1
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| #define OMAP2430_CONTROL_PADCONF_CAM_D11_OFFSET			0x0b2
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| #define OMAP2430_CONTROL_PADCONF_CAM_D10_OFFSET			0x0b3
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| #define OMAP2430_CONTROL_PADCONF_GPIO_134_OFFSET		0x0b4
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| #define OMAP2430_CONTROL_PADCONF_GPIO_135_OFFSET		0x0b5
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| #define OMAP2430_CONTROL_PADCONF_GPIO_136_OFFSET		0x0b6
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| #define OMAP2430_CONTROL_PADCONF_GPIO_137_OFFSET		0x0b7
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| #define OMAP2430_CONTROL_PADCONF_GPIO_138_OFFSET		0x0b8
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| #define OMAP2430_CONTROL_PADCONF_GPIO_139_OFFSET		0x0b9
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| #define OMAP2430_CONTROL_PADCONF_GPIO_140_OFFSET		0x0ba
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| #define OMAP2430_CONTROL_PADCONF_GPIO_141_OFFSET		0x0bb
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| #define OMAP2430_CONTROL_PADCONF_GPIO_142_OFFSET		0x0bc
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| #define OMAP2430_CONTROL_PADCONF_GPIO_154_OFFSET		0x0bd
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| #define OMAP2430_CONTROL_PADCONF_GPIO_148_OFFSET		0x0be
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| #define OMAP2430_CONTROL_PADCONF_GPIO_149_OFFSET		0x0bf
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| #define OMAP2430_CONTROL_PADCONF_GPIO_150_OFFSET		0x0c0
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| #define OMAP2430_CONTROL_PADCONF_GPIO_152_OFFSET		0x0c1
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| #define OMAP2430_CONTROL_PADCONF_GPIO_153_OFFSET		0x0c2
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| #define OMAP2430_CONTROL_PADCONF_SDMMC1_CLKO_OFFSET		0x0c3
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| #define OMAP2430_CONTROL_PADCONF_SDMMC1_CMD_OFFSET		0x0c4
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| #define OMAP2430_CONTROL_PADCONF_SDMMC1_DAT0_OFFSET		0x0c5
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| #define OMAP2430_CONTROL_PADCONF_SDMMC1_DAT1_OFFSET		0x0c6
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| #define OMAP2430_CONTROL_PADCONF_SDMMC1_DAT2_OFFSET		0x0c7
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| #define OMAP2430_CONTROL_PADCONF_SDMMC1_DAT3_OFFSET		0x0c8
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| #define OMAP2430_CONTROL_PADCONF_SDMMC2_CLKO_OFFSET		0x0c9
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| #define OMAP2430_CONTROL_PADCONF_SDMMC2_DAT3_OFFSET		0x0ca
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| #define OMAP2430_CONTROL_PADCONF_SDMMC2_CMD_OFFSET		0x0cb
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| #define OMAP2430_CONTROL_PADCONF_SDMMC2_DAT0_OFFSET		0x0cc
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| #define OMAP2430_CONTROL_PADCONF_SDMMC2_DAT2_OFFSET		0x0cd
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| #define OMAP2430_CONTROL_PADCONF_SDMMC2_DAT1_OFFSET		0x0ce
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| #define OMAP2430_CONTROL_PADCONF_UART2_CTS_OFFSET		0x0cf
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| #define OMAP2430_CONTROL_PADCONF_UART2_RTS_OFFSET		0x0d0
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| #define OMAP2430_CONTROL_PADCONF_UART2_TX_OFFSET		0x0d1
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| #define OMAP2430_CONTROL_PADCONF_UART2_RX_OFFSET		0x0d2
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| #define OMAP2430_CONTROL_PADCONF_MCBSP3_CLKX_OFFSET		0x0d3
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| #define OMAP2430_CONTROL_PADCONF_MCBSP3_FSX_OFFSET		0x0d4
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| #define OMAP2430_CONTROL_PADCONF_MCBSP3_DR_OFFSET		0x0d5
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| #define OMAP2430_CONTROL_PADCONF_MCBSP3_DX_OFFSET		0x0d6
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| #define OMAP2430_CONTROL_PADCONF_SSI1_DAT_TX_OFFSET		0x0d7
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| #define OMAP2430_CONTROL_PADCONF_SSI1_FLAG_TX_OFFSET		0x0d8
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| #define OMAP2430_CONTROL_PADCONF_SSI1_RDY_TX_OFFSET		0x0d9
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| #define OMAP2430_CONTROL_PADCONF_SSI1_DAT_RX_OFFSET		0x0da
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| #define OMAP2430_CONTROL_PADCONF_GPIO_63_OFFSET			0x0db
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| #define OMAP2430_CONTROL_PADCONF_SSI1_FLAG_RX_OFFSET		0x0dc
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| #define OMAP2430_CONTROL_PADCONF_SSI1_RDY_RX_OFFSET		0x0dd
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| #define OMAP2430_CONTROL_PADCONF_SSI1_WAKE_OFFSET		0x0de
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| #define OMAP2430_CONTROL_PADCONF_SPI1_CLK_OFFSET		0x0df
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| #define OMAP2430_CONTROL_PADCONF_SPI1_SIMO_OFFSET		0x0e0
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| #define OMAP2430_CONTROL_PADCONF_SPI1_SOMI_OFFSET		0x0e1
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| #define OMAP2430_CONTROL_PADCONF_SPI1_CS0_OFFSET		0x0e2
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| #define OMAP2430_CONTROL_PADCONF_SPI1_CS1_OFFSET		0x0e3
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| #define OMAP2430_CONTROL_PADCONF_SPI1_CS2_OFFSET		0x0e4
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| #define OMAP2430_CONTROL_PADCONF_SPI1_CS3_OFFSET		0x0e5
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| #define OMAP2430_CONTROL_PADCONF_SPI2_CLK_OFFSET		0x0e6
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| #define OMAP2430_CONTROL_PADCONF_SPI2_SIMO_OFFSET		0x0e7
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| #define OMAP2430_CONTROL_PADCONF_SPI2_SOMI_OFFSET		0x0e8
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| #define OMAP2430_CONTROL_PADCONF_SPI2_CS0_OFFSET		0x0e9
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| #define OMAP2430_CONTROL_PADCONF_MCBSP1_CLKR_OFFSET		0x0ea
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| #define OMAP2430_CONTROL_PADCONF_MCBSP1_FSR_OFFSET		0x0eb
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| #define OMAP2430_CONTROL_PADCONF_MCBSP1_DX_OFFSET		0x0ec
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| #define OMAP2430_CONTROL_PADCONF_MCBSP1_DR_OFFSET		0x0ed
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| #define OMAP2430_CONTROL_PADCONF_MCBSP_CLKS_OFFSET		0x0ee
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| #define OMAP2430_CONTROL_PADCONF_MCBSP1_FSX_OFFSET		0x0ef
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| #define OMAP2430_CONTROL_PADCONF_MCBSP1_CLKX_OFFSET		0x0f0
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| #define OMAP2430_CONTROL_PADCONF_I2C1_SCL_OFFSET		0x0f1
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| #define OMAP2430_CONTROL_PADCONF_I2C1_SDA_OFFSET		0x0f2
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| #define OMAP2430_CONTROL_PADCONF_I2C2_SCL_OFFSET		0x0f3
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| #define OMAP2430_CONTROL_PADCONF_I2C2_SDA_OFFSET		0x0f4
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| #define OMAP2430_CONTROL_PADCONF_HDQ_SIO_OFFSET			0x0f5
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| #define OMAP2430_CONTROL_PADCONF_UART3_CTS_RCTX_OFFSET		0x0f6
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| #define OMAP2430_CONTROL_PADCONF_UART3_RTS_SD_OFFSET		0x0f7
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| #define OMAP2430_CONTROL_PADCONF_UART3_TX_IRTX_OFFSET		0x0f8
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| #define OMAP2430_CONTROL_PADCONF_UART3_RX_IRRX_OFFSET		0x0f9
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| #define OMAP2430_CONTROL_PADCONF_GPIO_7_OFFSET			0x0fa
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| #define OMAP2430_CONTROL_PADCONF_GPIO_78_OFFSET			0x0fb
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| #define OMAP2430_CONTROL_PADCONF_GPIO_79_OFFSET			0x0fc
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| #define OMAP2430_CONTROL_PADCONF_GPIO_80_OFFSET			0x0fd
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| #define OMAP2430_CONTROL_PADCONF_GPIO_113_OFFSET		0x0fe
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| #define OMAP2430_CONTROL_PADCONF_GPIO_114_OFFSET		0x0ff
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| #define OMAP2430_CONTROL_PADCONF_GPIO_115_OFFSET		0x100
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| #define OMAP2430_CONTROL_PADCONF_GPIO_116_OFFSET		0x101
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| #define OMAP2430_CONTROL_PADCONF_SYS_DRM_MSECURE_OFFSET		0x102
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| #define OMAP2430_CONTROL_PADCONF_USB0HS_DATA3_OFFSET		0x103
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| #define OMAP2430_CONTROL_PADCONF_USB0HS_DATA4_OFFSET		0x104
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| #define OMAP2430_CONTROL_PADCONF_USB0HS_DATA5_OFFSET		0x105
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| #define OMAP2430_CONTROL_PADCONF_USB0HS_DATA6_OFFSET		0x106
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| #define OMAP2430_CONTROL_PADCONF_USB0HS_DATA2_OFFSET		0x107
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| #define OMAP2430_CONTROL_PADCONF_USB0HS_DATA0_OFFSET		0x108
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| #define OMAP2430_CONTROL_PADCONF_USB0HS_DATA1_OFFSET		0x109
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| #define OMAP2430_CONTROL_PADCONF_USB0HS_CLK_OFFSET		0x10a
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| #define OMAP2430_CONTROL_PADCONF_USB0HS_DIR_OFFSET		0x10b
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| #define OMAP2430_CONTROL_PADCONF_USB0HS_STP_OFFSET		0x10c
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| #define OMAP2430_CONTROL_PADCONF_USB0HS_NXT_OFFSET		0x10d
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| #define OMAP2430_CONTROL_PADCONF_USB0HS_DATA7_OFFSET		0x10e
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| #define OMAP2430_CONTROL_PADCONF_TV_OUT_OFFSET			0x10f
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| #define OMAP2430_CONTROL_PADCONF_TV_VREF_OFFSET			0x110
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| #define OMAP2430_CONTROL_PADCONF_TV_RSET_OFFSET			0x111
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| #define OMAP2430_CONTROL_PADCONF_TV_VFB_OFFSET			0x112
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| #define OMAP2430_CONTROL_PADCONF_TV_DACOUT_OFFSET		0x113
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| #define OMAP2430_CONTROL_PADCONF_AD2DMCAD0_OFFSET		0x114
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| #define OMAP2430_CONTROL_PADCONF_AD2DMCAD1_OFFSET		0x115
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| #define OMAP2430_CONTROL_PADCONF_AD2DMCAD2_OFFSET		0x116
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| #define OMAP2430_CONTROL_PADCONF_AD2DMCAD3_OFFSET		0x117
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| #define OMAP2430_CONTROL_PADCONF_AD2DMCAD4_OFFSET		0x118
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| #define OMAP2430_CONTROL_PADCONF_AD2DMCAD5_OFFSET		0x119
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| #define OMAP2430_CONTROL_PADCONF_AD2DMCAD6_OFFSET		0x11a
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| #define OMAP2430_CONTROL_PADCONF_AD2DMCAD7_OFFSET		0x11b
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| #define OMAP2430_CONTROL_PADCONF_AD2DMCAD8_OFFSET		0x11c
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| #define OMAP2430_CONTROL_PADCONF_AD2DMCAD9_OFFSET		0x11d
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| #define OMAP2430_CONTROL_PADCONF_AD2DMCAD10_OFFSET		0x11e
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| #define OMAP2430_CONTROL_PADCONF_AD2DMCAD11_OFFSET		0x11f
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| #define OMAP2430_CONTROL_PADCONF_AD2DMCAD12_OFFSET		0x120
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| #define OMAP2430_CONTROL_PADCONF_AD2DMCAD13_OFFSET		0x121
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| #define OMAP2430_CONTROL_PADCONF_AD2DMCAD14_OFFSET		0x122
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| #define OMAP2430_CONTROL_PADCONF_AD2DMCAD15_OFFSET		0x123
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| #define OMAP2430_CONTROL_PADCONF_AD2DMCAD16_OFFSET		0x124
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| #define OMAP2430_CONTROL_PADCONF_AD2DMCAD17_OFFSET		0x125
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| #define OMAP2430_CONTROL_PADCONF_AD2DMCAD18_OFFSET		0x126
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| #define OMAP2430_CONTROL_PADCONF_AD2DMCAD19_OFFSET		0x127
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| #define OMAP2430_CONTROL_PADCONF_AD2DMCAD20_OFFSET		0x128
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| #define OMAP2430_CONTROL_PADCONF_AD2DMCAD21_OFFSET		0x129
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| #define OMAP2430_CONTROL_PADCONF_AD2DMCAD22_OFFSET		0x12a
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| #define OMAP2430_CONTROL_PADCONF_AD2DMCAD23_OFFSET		0x12b
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| #define OMAP2430_CONTROL_PADCONF_AD2DMCAD24_OFFSET		0x12c
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| #define OMAP2430_CONTROL_PADCONF_AD2DMCAD25_OFFSET		0x12d
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| #define OMAP2430_CONTROL_PADCONF_AD2DMCAD26_OFFSET		0x12e
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| #define OMAP2430_CONTROL_PADCONF_AD2DMCAD27_OFFSET		0x12f
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| #define OMAP2430_CONTROL_PADCONF_AD2DMCAD28_OFFSET		0x130
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| #define OMAP2430_CONTROL_PADCONF_AD2DMCAD29_OFFSET		0x131
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| #define OMAP2430_CONTROL_PADCONF_AD2DMCAD30_OFFSET		0x132
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| #define OMAP2430_CONTROL_PADCONF_AD2DMCAD31_OFFSET		0x133
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| #define OMAP2430_CONTROL_PADCONF_AD2DMCAD32_OFFSET		0x134
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| #define OMAP2430_CONTROL_PADCONF_AD2DMCAD33_OFFSET		0x135
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| #define OMAP2430_CONTROL_PADCONF_AD2DMCAD34_OFFSET		0x136
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| #define OMAP2430_CONTROL_PADCONF_AD2DMCAD35_OFFSET		0x137
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| #define OMAP2430_CONTROL_PADCONF_AD2DMCAD36_OFFSET		0x138
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| #define OMAP2430_CONTROL_PADCONF_AD2DMCAD37_OFFSET		0x139
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| #define OMAP2430_CONTROL_PADCONF_AD2DMWRITE_OFFSET		0x13a
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| #define OMAP2430_CONTROL_PADCONF_D2DCLK26MI_OFFSET		0x13b
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| #define OMAP2430_CONTROL_PADCONF_D2DNRESPWRON1_OFFSET		0x13c
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| #define OMAP2430_CONTROL_PADCONF_D2DNRESWARM_OFFSET		0x13d
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| #define OMAP2430_CONTROL_PADCONF_D2DARM9NIRQ_OFFSET		0x13e
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| #define OMAP2430_CONTROL_PADCONF_D2DUMA2P6FIQ_OFFSET		0x13f
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| #define OMAP2430_CONTROL_PADCONF_D2DSPINT_OFFSET		0x140
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| #define OMAP2430_CONTROL_PADCONF_D2DFRINT_OFFSET		0x141
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| #define OMAP2430_CONTROL_PADCONF_D2DDMAREQ0_OFFSET		0x142
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| #define OMAP2430_CONTROL_PADCONF_D2DDMAREQ1_OFFSET		0x143
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| #define OMAP2430_CONTROL_PADCONF_D2DDMAREQ2_OFFSET		0x144
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| #define OMAP2430_CONTROL_PADCONF_D2DDMAREQ3_OFFSET		0x145
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| #define OMAP2430_CONTROL_PADCONF_D2DN3GTRST_OFFSET		0x146
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| #define OMAP2430_CONTROL_PADCONF_D2DN3GTDI_OFFSET		0x147
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| #define OMAP2430_CONTROL_PADCONF_D2DN3GTDO_OFFSET		0x148
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| #define OMAP2430_CONTROL_PADCONF_D2DN3GTMS_OFFSET		0x149
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| #define OMAP2430_CONTROL_PADCONF_D2DN3GTCK_OFFSET		0x14a
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| #define OMAP2430_CONTROL_PADCONF_D2DN3GRTCK_OFFSET		0x14b
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| #define OMAP2430_CONTROL_PADCONF_D2DMSTDBY_OFFSET		0x14c
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| #define OMAP2430_CONTROL_PADCONF_AD2DSREAD_OFFSET		0x14d
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| #define OMAP2430_CONTROL_PADCONF_D2DSWAKEUP_OFFSET		0x14e
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| #define OMAP2430_CONTROL_PADCONF_D2DIDLEREQ_OFFSET		0x14f
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| #define OMAP2430_CONTROL_PADCONF_D2DIDLEACK_OFFSET		0x150
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| #define OMAP2430_CONTROL_PADCONF_D2DSPARE0_OFFSET		0x151
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| #define OMAP2430_CONTROL_PADCONF_AD2DSWRITE_OFFSET		0x152
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| #define OMAP2430_CONTROL_PADCONF_AD2DMREAD_OFFSET		0x153
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| 
 | |
| #define OMAP2430_CONTROL_PADCONF_MUX_SIZE			\
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| 		(OMAP2430_CONTROL_PADCONF_AD2DMREAD_OFFSET + 0x1)
 |