 a5f6ea29f9
			
		
	
	
	a5f6ea29f9
	
	
	
		
			
			Commit bcf24e1daa ("mmc: omap_hsmmc: use the generic config for
omap2plus devices"), enabled the build for other platforms for compile
testing.
sh-allmodconfig now fails with:
    include/linux/omap-dma.h:171:8: error: expected identifier before numeric constant
    make[4]: *** [drivers/mmc/host/omap_hsmmc.o] Error 1
This happens because SuperH #defines "CCR", which is one of the enum
values in include/linux/omap-dma.h.  There's a similar issue with "CCR2"
on sh2a.
As "CCR" and "CCR2" are too generic names for global #defines, prefix
them with "SH_" to fix this.
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
		
	
			
		
			
				
	
	
		
			189 lines
		
	
	
	
		
			4.6 KiB
			
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			189 lines
		
	
	
	
		
			4.6 KiB
			
		
	
	
	
		
			C
		
	
	
	
	
	
| /*
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|  * arch/sh/mm/cache-sh2a.c
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|  *
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|  * Copyright (C) 2008 Yoshinori Sato
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|  *
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|  * Released under the terms of the GNU GPL v2.0.
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|  */
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| 
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| #include <linux/init.h>
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| #include <linux/mm.h>
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| 
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| #include <asm/cache.h>
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| #include <asm/addrspace.h>
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| #include <asm/processor.h>
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| #include <asm/cacheflush.h>
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| #include <asm/io.h>
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| 
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| /*
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|  * The maximum number of pages we support up to when doing ranged dcache
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|  * flushing. Anything exceeding this will simply flush the dcache in its
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|  * entirety.
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|  */
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| #define MAX_OCACHE_PAGES	32
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| #define MAX_ICACHE_PAGES	32
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| 
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| #ifdef CONFIG_CACHE_WRITEBACK
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| static void sh2a_flush_oc_line(unsigned long v, int way)
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| {
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| 	unsigned long addr = (v & 0x000007f0) | (way << 11);
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| 	unsigned long data;
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| 
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| 	data = __raw_readl(CACHE_OC_ADDRESS_ARRAY | addr);
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| 	if ((data & CACHE_PHYSADDR_MASK) == (v & CACHE_PHYSADDR_MASK)) {
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| 		data &= ~SH_CACHE_UPDATED;
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| 		__raw_writel(data, CACHE_OC_ADDRESS_ARRAY | addr);
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| 	}
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| }
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| #endif
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| 
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| static void sh2a_invalidate_line(unsigned long cache_addr, unsigned long v)
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| {
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| 	/* Set associative bit to hit all ways */
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| 	unsigned long addr = (v & 0x000007f0) | SH_CACHE_ASSOC;
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| 	__raw_writel((addr & CACHE_PHYSADDR_MASK), cache_addr | addr);
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| }
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| 
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| /*
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|  * Write back the dirty D-caches, but not invalidate them.
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|  */
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| static void sh2a__flush_wback_region(void *start, int size)
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| {
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| #ifdef CONFIG_CACHE_WRITEBACK
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| 	unsigned long v;
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| 	unsigned long begin, end;
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| 	unsigned long flags;
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| 	int nr_ways;
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| 
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| 	begin = (unsigned long)start & ~(L1_CACHE_BYTES-1);
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| 	end = ((unsigned long)start + size + L1_CACHE_BYTES-1)
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| 		& ~(L1_CACHE_BYTES-1);
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| 	nr_ways = current_cpu_data.dcache.ways;
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| 
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| 	local_irq_save(flags);
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| 	jump_to_uncached();
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| 
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| 	/* If there are too many pages then flush the entire cache */
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| 	if (((end - begin) >> PAGE_SHIFT) >= MAX_OCACHE_PAGES) {
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| 		begin = CACHE_OC_ADDRESS_ARRAY;
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| 		end = begin + (nr_ways * current_cpu_data.dcache.way_size);
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| 
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| 		for (v = begin; v < end; v += L1_CACHE_BYTES) {
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| 			unsigned long data = __raw_readl(v);
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| 			if (data & SH_CACHE_UPDATED)
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| 				__raw_writel(data & ~SH_CACHE_UPDATED, v);
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| 		}
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| 	} else {
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| 		int way;
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| 		for (way = 0; way < nr_ways; way++) {
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| 			for (v = begin; v < end; v += L1_CACHE_BYTES)
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| 				sh2a_flush_oc_line(v, way);
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| 		}
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| 	}
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| 
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| 	back_to_cached();
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| 	local_irq_restore(flags);
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| #endif
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| }
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| 
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| /*
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|  * Write back the dirty D-caches and invalidate them.
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|  */
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| static void sh2a__flush_purge_region(void *start, int size)
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| {
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| 	unsigned long v;
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| 	unsigned long begin, end;
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| 	unsigned long flags;
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| 
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| 	begin = (unsigned long)start & ~(L1_CACHE_BYTES-1);
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| 	end = ((unsigned long)start + size + L1_CACHE_BYTES-1)
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| 		& ~(L1_CACHE_BYTES-1);
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| 
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| 	local_irq_save(flags);
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| 	jump_to_uncached();
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| 
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| 	for (v = begin; v < end; v+=L1_CACHE_BYTES) {
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| #ifdef CONFIG_CACHE_WRITEBACK
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| 		int way;
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| 		int nr_ways = current_cpu_data.dcache.ways;
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| 		for (way = 0; way < nr_ways; way++)
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| 			sh2a_flush_oc_line(v, way);
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| #endif
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| 		sh2a_invalidate_line(CACHE_OC_ADDRESS_ARRAY, v);
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| 	}
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| 
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| 	back_to_cached();
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| 	local_irq_restore(flags);
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| }
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| 
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| /*
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|  * Invalidate the D-caches, but no write back please
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|  */
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| static void sh2a__flush_invalidate_region(void *start, int size)
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| {
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| 	unsigned long v;
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| 	unsigned long begin, end;
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| 	unsigned long flags;
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| 
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| 	begin = (unsigned long)start & ~(L1_CACHE_BYTES-1);
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| 	end = ((unsigned long)start + size + L1_CACHE_BYTES-1)
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| 		& ~(L1_CACHE_BYTES-1);
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| 
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| 	local_irq_save(flags);
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| 	jump_to_uncached();
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| 
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| 	/* If there are too many pages then just blow the cache */
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| 	if (((end - begin) >> PAGE_SHIFT) >= MAX_OCACHE_PAGES) {
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| 		__raw_writel(__raw_readl(SH_CCR) | CCR_OCACHE_INVALIDATE,
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| 			     SH_CCR);
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| 	} else {
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| 		for (v = begin; v < end; v += L1_CACHE_BYTES)
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| 			sh2a_invalidate_line(CACHE_OC_ADDRESS_ARRAY, v);
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| 	}
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| 
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| 	back_to_cached();
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| 	local_irq_restore(flags);
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| }
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| 
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| /*
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|  * Write back the range of D-cache, and purge the I-cache.
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|  */
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| static void sh2a_flush_icache_range(void *args)
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| {
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| 	struct flusher_data *data = args;
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| 	unsigned long start, end;
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| 	unsigned long v;
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| 	unsigned long flags;
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| 
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| 	start = data->addr1 & ~(L1_CACHE_BYTES-1);
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| 	end = (data->addr2 + L1_CACHE_BYTES-1) & ~(L1_CACHE_BYTES-1);
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| 
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| #ifdef CONFIG_CACHE_WRITEBACK
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| 	sh2a__flush_wback_region((void *)start, end-start);
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| #endif
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| 
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| 	local_irq_save(flags);
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| 	jump_to_uncached();
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| 
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| 	/* I-Cache invalidate */
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| 	/* If there are too many pages then just blow the cache */
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| 	if (((end - start) >> PAGE_SHIFT) >= MAX_ICACHE_PAGES) {
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| 		__raw_writel(__raw_readl(SH_CCR) | CCR_ICACHE_INVALIDATE,
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| 			     SH_CCR);
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| 	} else {
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| 		for (v = start; v < end; v += L1_CACHE_BYTES)
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| 			sh2a_invalidate_line(CACHE_IC_ADDRESS_ARRAY, v);
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| 	}
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| 
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| 	back_to_cached();
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| 	local_irq_restore(flags);
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| }
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| 
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| void __init sh2a_cache_init(void)
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| {
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| 	local_flush_icache_range	= sh2a_flush_icache_range;
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| 
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| 	__flush_wback_region		= sh2a__flush_wback_region;
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| 	__flush_purge_region		= sh2a__flush_purge_region;
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| 	__flush_invalidate_region	= sh2a__flush_invalidate_region;
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| }
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