8fc5ec7044
In commit c441d4a54c ("MIPS: mm: Only build one microassembler that
is suitable"), the Makefile at arch/mips/mm was rewritten to only
build the "right" microassembler file, depending on whether
CONFIG_CPU_MICROMIPS is set or not.
In the files, however, there are still preprocessor definitions
depending on CONFIG_CPU_MICROMIPS. The #ifdef around them can now
never evaluate to true, so let's remove them altogether.
This inconsistency was found using the undertaker-checkpatch tool.
Signed-off-by: Andreas Ruprecht <rupran@einserver.de>
Reviewed-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: Valentin Rothberg <valentinrothberg@gmail.com>
Cc: Paul Bolle <pebolle@tiscali.nl>
Patchwork: https://patchwork.linux-mips.org/patch/9267/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
227 lines
7.8 KiB
C
227 lines
7.8 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* A small micro-assembler. It is intentionally kept simple, does only
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* support a subset of instructions, and does not try to hide pipeline
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* effects like branch delay slots.
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*
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* Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer
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* Copyright (C) 2005, 2007 Maciej W. Rozycki
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* Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
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* Copyright (C) 2012, 2013 MIPS Technologies, Inc. All rights reserved.
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*/
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <asm/inst.h>
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#include <asm/elf.h>
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#include <asm/bugs.h>
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#define UASM_ISA _UASM_ISA_MICROMIPS
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#include <asm/uasm.h>
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#define RS_MASK 0x1f
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#define RS_SH 16
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#define RT_MASK 0x1f
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#define RT_SH 21
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#define SCIMM_MASK 0x3ff
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#define SCIMM_SH 16
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/* This macro sets the non-variable bits of an instruction. */
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#define M(a, b, c, d, e, f) \
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((a) << OP_SH \
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| (b) << RT_SH \
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| (c) << RS_SH \
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| (d) << RD_SH \
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| (e) << RE_SH \
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| (f) << FUNC_SH)
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#include "uasm.c"
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static struct insn insn_table_MM[] = {
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{ insn_addu, M(mm_pool32a_op, 0, 0, 0, 0, mm_addu32_op), RT | RS | RD },
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{ insn_addiu, M(mm_addiu32_op, 0, 0, 0, 0, 0), RT | RS | SIMM },
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{ insn_and, M(mm_pool32a_op, 0, 0, 0, 0, mm_and_op), RT | RS | RD },
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{ insn_andi, M(mm_andi32_op, 0, 0, 0, 0, 0), RT | RS | UIMM },
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{ insn_beq, M(mm_beq32_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
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{ insn_beql, 0, 0 },
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{ insn_bgez, M(mm_pool32i_op, mm_bgez_op, 0, 0, 0, 0), RS | BIMM },
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{ insn_bgezl, 0, 0 },
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{ insn_bltz, M(mm_pool32i_op, mm_bltz_op, 0, 0, 0, 0), RS | BIMM },
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{ insn_bltzl, 0, 0 },
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{ insn_bne, M(mm_bne32_op, 0, 0, 0, 0, 0), RT | RS | BIMM },
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{ insn_cache, M(mm_pool32b_op, 0, 0, mm_cache_func, 0, 0), RT | RS | SIMM },
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{ insn_daddu, 0, 0 },
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{ insn_daddiu, 0, 0 },
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{ insn_divu, M(mm_pool32a_op, 0, 0, 0, mm_divu_op, mm_pool32axf_op), RT | RS },
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{ insn_dmfc0, 0, 0 },
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{ insn_dmtc0, 0, 0 },
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{ insn_dsll, 0, 0 },
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{ insn_dsll32, 0, 0 },
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{ insn_dsra, 0, 0 },
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{ insn_dsrl, 0, 0 },
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{ insn_dsrl32, 0, 0 },
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{ insn_drotr, 0, 0 },
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{ insn_drotr32, 0, 0 },
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{ insn_dsubu, 0, 0 },
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{ insn_eret, M(mm_pool32a_op, 0, 0, 0, mm_eret_op, mm_pool32axf_op), 0 },
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{ insn_ins, M(mm_pool32a_op, 0, 0, 0, 0, mm_ins_op), RT | RS | RD | RE },
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{ insn_ext, M(mm_pool32a_op, 0, 0, 0, 0, mm_ext_op), RT | RS | RD | RE },
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{ insn_j, M(mm_j32_op, 0, 0, 0, 0, 0), JIMM },
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{ insn_jal, M(mm_jal32_op, 0, 0, 0, 0, 0), JIMM },
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{ insn_jalr, M(mm_pool32a_op, 0, 0, 0, mm_jalr_op, mm_pool32axf_op), RT | RS },
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{ insn_jr, M(mm_pool32a_op, 0, 0, 0, mm_jalr_op, mm_pool32axf_op), RS },
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{ insn_lb, M(mm_lb32_op, 0, 0, 0, 0, 0), RT | RS | SIMM },
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{ insn_ld, 0, 0 },
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{ insn_lh, M(mm_lh32_op, 0, 0, 0, 0, 0), RS | RS | SIMM },
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{ insn_ll, M(mm_pool32c_op, 0, 0, (mm_ll_func << 1), 0, 0), RS | RT | SIMM },
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{ insn_lld, 0, 0 },
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{ insn_lui, M(mm_pool32i_op, mm_lui_op, 0, 0, 0, 0), RS | SIMM },
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{ insn_lw, M(mm_lw32_op, 0, 0, 0, 0, 0), RT | RS | SIMM },
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{ insn_mfc0, M(mm_pool32a_op, 0, 0, 0, mm_mfc0_op, mm_pool32axf_op), RT | RS | RD },
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{ insn_mfhi, M(mm_pool32a_op, 0, 0, 0, mm_mfhi32_op, mm_pool32axf_op), RS },
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{ insn_mflo, M(mm_pool32a_op, 0, 0, 0, mm_mflo32_op, mm_pool32axf_op), RS },
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{ insn_mtc0, M(mm_pool32a_op, 0, 0, 0, mm_mtc0_op, mm_pool32axf_op), RT | RS | RD },
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{ insn_mul, M(mm_pool32a_op, 0, 0, 0, 0, mm_mul_op), RT | RS | RD },
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{ insn_or, M(mm_pool32a_op, 0, 0, 0, 0, mm_or32_op), RT | RS | RD },
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{ insn_ori, M(mm_ori32_op, 0, 0, 0, 0, 0), RT | RS | UIMM },
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{ insn_pref, M(mm_pool32c_op, 0, 0, (mm_pref_func << 1), 0, 0), RT | RS | SIMM },
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{ insn_rfe, 0, 0 },
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{ insn_sc, M(mm_pool32c_op, 0, 0, (mm_sc_func << 1), 0, 0), RT | RS | SIMM },
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{ insn_scd, 0, 0 },
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{ insn_sd, 0, 0 },
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{ insn_sll, M(mm_pool32a_op, 0, 0, 0, 0, mm_sll32_op), RT | RS | RD },
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{ insn_sllv, M(mm_pool32a_op, 0, 0, 0, 0, mm_sllv32_op), RT | RS | RD },
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{ insn_slt, M(mm_pool32a_op, 0, 0, 0, 0, mm_slt_op), RT | RS | RD },
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{ insn_sltiu, M(mm_sltiu32_op, 0, 0, 0, 0, 0), RT | RS | SIMM },
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{ insn_sltu, M(mm_pool32a_op, 0, 0, 0, 0, mm_sltu_op), RT | RS | RD },
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{ insn_sra, M(mm_pool32a_op, 0, 0, 0, 0, mm_sra_op), RT | RS | RD },
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{ insn_srl, M(mm_pool32a_op, 0, 0, 0, 0, mm_srl32_op), RT | RS | RD },
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{ insn_srlv, M(mm_pool32a_op, 0, 0, 0, 0, mm_srlv32_op), RT | RS | RD },
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{ insn_rotr, M(mm_pool32a_op, 0, 0, 0, 0, mm_rotr_op), RT | RS | RD },
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{ insn_subu, M(mm_pool32a_op, 0, 0, 0, 0, mm_subu32_op), RT | RS | RD },
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{ insn_sw, M(mm_sw32_op, 0, 0, 0, 0, 0), RT | RS | SIMM },
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{ insn_sync, M(mm_pool32a_op, 0, 0, 0, mm_sync_op, mm_pool32axf_op), RS },
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{ insn_tlbp, M(mm_pool32a_op, 0, 0, 0, mm_tlbp_op, mm_pool32axf_op), 0 },
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{ insn_tlbr, M(mm_pool32a_op, 0, 0, 0, mm_tlbr_op, mm_pool32axf_op), 0 },
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{ insn_tlbwi, M(mm_pool32a_op, 0, 0, 0, mm_tlbwi_op, mm_pool32axf_op), 0 },
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{ insn_tlbwr, M(mm_pool32a_op, 0, 0, 0, mm_tlbwr_op, mm_pool32axf_op), 0 },
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{ insn_wait, M(mm_pool32a_op, 0, 0, 0, mm_wait_op, mm_pool32axf_op), SCIMM },
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{ insn_wsbh, M(mm_pool32a_op, 0, 0, 0, mm_wsbh_op, mm_pool32axf_op), RT | RS },
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{ insn_xor, M(mm_pool32a_op, 0, 0, 0, 0, mm_xor32_op), RT | RS | RD },
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{ insn_xori, M(mm_xori32_op, 0, 0, 0, 0, 0), RT | RS | UIMM },
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{ insn_dins, 0, 0 },
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{ insn_dinsm, 0, 0 },
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{ insn_syscall, M(mm_pool32a_op, 0, 0, 0, mm_syscall_op, mm_pool32axf_op), SCIMM},
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{ insn_bbit0, 0, 0 },
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{ insn_bbit1, 0, 0 },
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{ insn_lwx, 0, 0 },
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{ insn_ldx, 0, 0 },
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{ insn_invalid, 0, 0 }
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};
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#undef M
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static inline u32 build_bimm(s32 arg)
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{
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WARN(arg > 0xffff || arg < -0x10000,
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KERN_WARNING "Micro-assembler field overflow\n");
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WARN(arg & 0x3, KERN_WARNING "Invalid micro-assembler branch target\n");
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return ((arg < 0) ? (1 << 15) : 0) | ((arg >> 1) & 0x7fff);
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}
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static inline u32 build_jimm(u32 arg)
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{
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WARN(arg & ~((JIMM_MASK << 2) | 1),
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KERN_WARNING "Micro-assembler field overflow\n");
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return (arg >> 1) & JIMM_MASK;
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}
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/*
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* The order of opcode arguments is implicitly left to right,
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* starting with RS and ending with FUNC or IMM.
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*/
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static void build_insn(u32 **buf, enum opcode opc, ...)
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{
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struct insn *ip = NULL;
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unsigned int i;
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va_list ap;
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u32 op;
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for (i = 0; insn_table_MM[i].opcode != insn_invalid; i++)
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if (insn_table_MM[i].opcode == opc) {
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ip = &insn_table_MM[i];
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break;
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}
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if (!ip || (opc == insn_daddiu && r4k_daddiu_bug()))
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panic("Unsupported Micro-assembler instruction %d", opc);
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op = ip->match;
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va_start(ap, opc);
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if (ip->fields & RS) {
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if (opc == insn_mfc0 || opc == insn_mtc0)
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op |= build_rt(va_arg(ap, u32));
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else
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op |= build_rs(va_arg(ap, u32));
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}
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if (ip->fields & RT) {
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if (opc == insn_mfc0 || opc == insn_mtc0)
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op |= build_rs(va_arg(ap, u32));
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else
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op |= build_rt(va_arg(ap, u32));
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}
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if (ip->fields & RD)
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op |= build_rd(va_arg(ap, u32));
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if (ip->fields & RE)
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op |= build_re(va_arg(ap, u32));
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if (ip->fields & SIMM)
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op |= build_simm(va_arg(ap, s32));
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if (ip->fields & UIMM)
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op |= build_uimm(va_arg(ap, u32));
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if (ip->fields & BIMM)
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op |= build_bimm(va_arg(ap, s32));
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if (ip->fields & JIMM)
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op |= build_jimm(va_arg(ap, u32));
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if (ip->fields & FUNC)
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op |= build_func(va_arg(ap, u32));
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if (ip->fields & SET)
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op |= build_set(va_arg(ap, u32));
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if (ip->fields & SCIMM)
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op |= build_scimm(va_arg(ap, u32));
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va_end(ap);
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#ifdef CONFIG_CPU_LITTLE_ENDIAN
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**buf = ((op & 0xffff) << 16) | (op >> 16);
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#else
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**buf = op;
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#endif
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(*buf)++;
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}
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static inline void
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__resolve_relocs(struct uasm_reloc *rel, struct uasm_label *lab)
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{
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long laddr = (long)lab->addr;
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long raddr = (long)rel->addr;
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switch (rel->type) {
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case R_MIPS_PC16:
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#ifdef CONFIG_CPU_LITTLE_ENDIAN
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*rel->addr |= (build_bimm(laddr - (raddr + 4)) << 16);
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#else
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*rel->addr |= build_bimm(laddr - (raddr + 4));
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#endif
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break;
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default:
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panic("Unsupported Micro-assembler relocation %d",
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rel->type);
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}
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}
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