8922bc3058
Branch insn can't be scheduled as last insn of Zero Overhead loop Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
152 lines
2.6 KiB
ArmAsm
152 lines
2.6 KiB
ArmAsm
/*
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* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/linkage.h>
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#ifdef __LITTLE_ENDIAN__
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#define WORD2 r2
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#define SHIFT r3
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#else /* BIG ENDIAN */
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#define WORD2 r3
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#define SHIFT r2
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#endif
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ENTRY(memcmp)
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or r12,r0,r1
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asl_s r12,r12,30
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sub r3,r2,1
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brls r2,r12,.Lbytewise
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ld r4,[r0,0]
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ld r5,[r1,0]
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lsr.f lp_count,r3,3
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#ifdef CONFIG_ISA_ARCV2
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/* In ARCv2 a branch can't be the last instruction in a zero overhead
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* loop.
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* So we move the branch to the start of the loop, duplicate it
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* after the end, and set up r12 so that the branch isn't taken
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* initially.
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*/
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mov_s r12,WORD2
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lpne .Loop_end
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brne WORD2,r12,.Lodd
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ld WORD2,[r0,4]
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#else
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lpne .Loop_end
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ld_s WORD2,[r0,4]
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#endif
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ld_s r12,[r1,4]
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brne r4,r5,.Leven
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ld.a r4,[r0,8]
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ld.a r5,[r1,8]
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#ifdef CONFIG_ISA_ARCV2
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.Loop_end:
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brne WORD2,r12,.Lodd
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#else
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brne WORD2,r12,.Lodd
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.Loop_end:
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#endif
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asl_s SHIFT,SHIFT,3
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bhs_s .Last_cmp
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brne r4,r5,.Leven
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ld r4,[r0,4]
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ld r5,[r1,4]
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#ifdef __LITTLE_ENDIAN__
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nop_s
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; one more load latency cycle
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.Last_cmp:
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xor r0,r4,r5
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bset r0,r0,SHIFT
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sub_s r1,r0,1
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bic_s r1,r1,r0
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norm r1,r1
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b.d .Leven_cmp
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and r1,r1,24
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.Leven:
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xor r0,r4,r5
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sub_s r1,r0,1
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bic_s r1,r1,r0
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norm r1,r1
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; slow track insn
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and r1,r1,24
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.Leven_cmp:
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asl r2,r4,r1
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asl r12,r5,r1
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lsr_s r2,r2,1
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lsr_s r12,r12,1
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j_s.d [blink]
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sub r0,r2,r12
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.balign 4
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.Lodd:
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xor r0,WORD2,r12
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sub_s r1,r0,1
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bic_s r1,r1,r0
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norm r1,r1
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; slow track insn
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and r1,r1,24
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asl_s r2,r2,r1
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asl_s r12,r12,r1
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lsr_s r2,r2,1
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lsr_s r12,r12,1
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j_s.d [blink]
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sub r0,r2,r12
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#else /* BIG ENDIAN */
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.Last_cmp:
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neg_s SHIFT,SHIFT
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lsr r4,r4,SHIFT
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lsr r5,r5,SHIFT
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; slow track insn
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.Leven:
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sub.f r0,r4,r5
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mov.ne r0,1
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j_s.d [blink]
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bset.cs r0,r0,31
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.Lodd:
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cmp_s WORD2,r12
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mov_s r0,1
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j_s.d [blink]
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bset.cs r0,r0,31
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#endif /* ENDIAN */
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.balign 4
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.Lbytewise:
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breq r2,0,.Lnil
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ldb r4,[r0,0]
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ldb r5,[r1,0]
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lsr.f lp_count,r3
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#ifdef CONFIG_ISA_ARCV2
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mov r12,r3
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lpne .Lbyte_end
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brne r3,r12,.Lbyte_odd
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#else
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lpne .Lbyte_end
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#endif
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ldb_s r3,[r0,1]
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ldb r12,[r1,1]
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brne r4,r5,.Lbyte_even
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ldb.a r4,[r0,2]
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ldb.a r5,[r1,2]
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#ifdef CONFIG_ISA_ARCV2
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.Lbyte_end:
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brne r3,r12,.Lbyte_odd
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#else
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brne r3,r12,.Lbyte_odd
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.Lbyte_end:
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#endif
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bcc .Lbyte_even
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brne r4,r5,.Lbyte_even
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ldb_s r3,[r0,1]
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ldb_s r12,[r1,1]
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.Lbyte_odd:
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j_s.d [blink]
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sub r0,r3,r12
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.Lbyte_even:
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j_s.d [blink]
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sub r0,r4,r5
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.Lnil:
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j_s.d [blink]
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mov r0,0
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END(memcmp)
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