126ae9adc1
The default cache operations for ARM64 were changed during 3.15. To use coherent operations a "dma-coherent" device tree property is required. If that property is not present in the device tree node then the non-coherent operations are assigned for the device. Add support to the ccp driver to assign the AXI DMA cache settings based on whether the "dma-coherent" property is present in the device node. If present, use settings that work with the caches. If not present, use settings that do not look at the caches. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
280 lines
6.7 KiB
C
280 lines
6.7 KiB
C
/*
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* AMD Cryptographic Coprocessor (CCP) driver
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*
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* Copyright (C) 2013 Advanced Micro Devices, Inc.
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*
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* Author: Tom Lendacky <thomas.lendacky@amd.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __CCP_DEV_H__
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#define __CCP_DEV_H__
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#include <linux/device.h>
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#include <linux/pci.h>
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#include <linux/spinlock.h>
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#include <linux/mutex.h>
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#include <linux/list.h>
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#include <linux/wait.h>
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#include <linux/dmapool.h>
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#include <linux/hw_random.h>
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#define MAX_DMAPOOL_NAME_LEN 32
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#define MAX_HW_QUEUES 5
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#define MAX_CMD_QLEN 100
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#define TRNG_RETRIES 10
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#define CACHE_NONE 0x00
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#define CACHE_WB_NO_ALLOC 0xb7
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/****** Register Mappings ******/
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#define Q_MASK_REG 0x000
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#define TRNG_OUT_REG 0x00c
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#define IRQ_MASK_REG 0x040
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#define IRQ_STATUS_REG 0x200
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#define DEL_CMD_Q_JOB 0x124
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#define DEL_Q_ACTIVE 0x00000200
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#define DEL_Q_ID_SHIFT 6
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#define CMD_REQ0 0x180
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#define CMD_REQ_INCR 0x04
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#define CMD_Q_STATUS_BASE 0x210
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#define CMD_Q_INT_STATUS_BASE 0x214
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#define CMD_Q_STATUS_INCR 0x20
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#define CMD_Q_CACHE_BASE 0x228
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#define CMD_Q_CACHE_INC 0x20
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#define CMD_Q_ERROR(__qs) ((__qs) & 0x0000003f);
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#define CMD_Q_DEPTH(__qs) (((__qs) >> 12) & 0x0000000f);
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/****** REQ0 Related Values ******/
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#define REQ0_WAIT_FOR_WRITE 0x00000004
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#define REQ0_INT_ON_COMPLETE 0x00000002
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#define REQ0_STOP_ON_COMPLETE 0x00000001
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#define REQ0_CMD_Q_SHIFT 9
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#define REQ0_JOBID_SHIFT 3
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/****** REQ1 Related Values ******/
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#define REQ1_PROTECT_SHIFT 27
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#define REQ1_ENGINE_SHIFT 23
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#define REQ1_KEY_KSB_SHIFT 2
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#define REQ1_EOM 0x00000002
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#define REQ1_INIT 0x00000001
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/* AES Related Values */
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#define REQ1_AES_TYPE_SHIFT 21
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#define REQ1_AES_MODE_SHIFT 18
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#define REQ1_AES_ACTION_SHIFT 17
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#define REQ1_AES_CFB_SIZE_SHIFT 10
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/* XTS-AES Related Values */
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#define REQ1_XTS_AES_SIZE_SHIFT 10
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/* SHA Related Values */
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#define REQ1_SHA_TYPE_SHIFT 21
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/* RSA Related Values */
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#define REQ1_RSA_MOD_SIZE_SHIFT 10
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/* Pass-Through Related Values */
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#define REQ1_PT_BW_SHIFT 12
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#define REQ1_PT_BS_SHIFT 10
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/* ECC Related Values */
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#define REQ1_ECC_AFFINE_CONVERT 0x00200000
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#define REQ1_ECC_FUNCTION_SHIFT 18
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/****** REQ4 Related Values ******/
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#define REQ4_KSB_SHIFT 18
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#define REQ4_MEMTYPE_SHIFT 16
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/****** REQ6 Related Values ******/
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#define REQ6_MEMTYPE_SHIFT 16
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/****** Key Storage Block ******/
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#define KSB_START 77
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#define KSB_END 127
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#define KSB_COUNT (KSB_END - KSB_START + 1)
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#define CCP_KSB_BITS 256
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#define CCP_KSB_BYTES 32
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#define CCP_JOBID_MASK 0x0000003f
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#define CCP_DMAPOOL_MAX_SIZE 64
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#define CCP_DMAPOOL_ALIGN (1 << 5)
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#define CCP_REVERSE_BUF_SIZE 64
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#define CCP_AES_KEY_KSB_COUNT 1
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#define CCP_AES_CTX_KSB_COUNT 1
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#define CCP_XTS_AES_KEY_KSB_COUNT 1
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#define CCP_XTS_AES_CTX_KSB_COUNT 1
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#define CCP_SHA_KSB_COUNT 1
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#define CCP_RSA_MAX_WIDTH 4096
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#define CCP_PASSTHRU_BLOCKSIZE 256
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#define CCP_PASSTHRU_MASKSIZE 32
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#define CCP_PASSTHRU_KSB_COUNT 1
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#define CCP_ECC_MODULUS_BYTES 48 /* 384-bits */
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#define CCP_ECC_MAX_OPERANDS 6
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#define CCP_ECC_MAX_OUTPUTS 3
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#define CCP_ECC_SRC_BUF_SIZE 448
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#define CCP_ECC_DST_BUF_SIZE 192
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#define CCP_ECC_OPERAND_SIZE 64
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#define CCP_ECC_OUTPUT_SIZE 64
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#define CCP_ECC_RESULT_OFFSET 60
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#define CCP_ECC_RESULT_SUCCESS 0x0001
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struct ccp_device;
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struct ccp_cmd;
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struct ccp_cmd_queue {
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struct ccp_device *ccp;
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/* Queue identifier */
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u32 id;
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/* Queue dma pool */
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struct dma_pool *dma_pool;
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/* Queue reserved KSB regions */
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u32 ksb_key;
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u32 ksb_ctx;
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/* Queue processing thread */
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struct task_struct *kthread;
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unsigned int active;
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unsigned int suspended;
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/* Number of free command slots available */
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unsigned int free_slots;
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/* Interrupt masks */
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u32 int_ok;
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u32 int_err;
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/* Register addresses for queue */
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void __iomem *reg_status;
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void __iomem *reg_int_status;
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/* Status values from job */
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u32 int_status;
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u32 q_status;
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u32 q_int_status;
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u32 cmd_error;
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/* Interrupt wait queue */
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wait_queue_head_t int_queue;
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unsigned int int_rcvd;
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} ____cacheline_aligned;
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struct ccp_device {
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struct device *dev;
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/*
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* Bus specific device information
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*/
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void *dev_specific;
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int (*get_irq)(struct ccp_device *ccp);
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void (*free_irq)(struct ccp_device *ccp);
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unsigned int irq;
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/*
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* I/O area used for device communication. The register mapping
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* starts at an offset into the mapped bar.
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* The CMD_REQx registers and the Delete_Cmd_Queue_Job register
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* need to be protected while a command queue thread is accessing
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* them.
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*/
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struct mutex req_mutex ____cacheline_aligned;
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void __iomem *io_map;
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void __iomem *io_regs;
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/*
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* Master lists that all cmds are queued on. Because there can be
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* more than one CCP command queue that can process a cmd a separate
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* backlog list is neeeded so that the backlog completion call
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* completes before the cmd is available for execution.
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*/
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spinlock_t cmd_lock ____cacheline_aligned;
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unsigned int cmd_count;
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struct list_head cmd;
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struct list_head backlog;
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/*
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* The command queues. These represent the queues available on the
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* CCP that are available for processing cmds
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*/
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struct ccp_cmd_queue cmd_q[MAX_HW_QUEUES];
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unsigned int cmd_q_count;
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/*
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* Support for the CCP True RNG
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*/
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struct hwrng hwrng;
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unsigned int hwrng_retries;
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/*
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* A counter used to generate job-ids for cmds submitted to the CCP
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*/
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atomic_t current_id ____cacheline_aligned;
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/*
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* The CCP uses key storage blocks (KSB) to maintain context for certain
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* operations. To prevent multiple cmds from using the same KSB range
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* a command queue reserves a KSB range for the duration of the cmd.
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* Each queue, will however, reserve 2 KSB blocks for operations that
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* only require single KSB entries (eg. AES context/iv and key) in order
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* to avoid allocation contention. This will reserve at most 10 KSB
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* entries, leaving 40 KSB entries available for dynamic allocation.
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*/
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struct mutex ksb_mutex ____cacheline_aligned;
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DECLARE_BITMAP(ksb, KSB_COUNT);
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wait_queue_head_t ksb_queue;
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unsigned int ksb_avail;
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unsigned int ksb_count;
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u32 ksb_start;
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/* Suspend support */
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unsigned int suspending;
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wait_queue_head_t suspend_queue;
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/* DMA caching attribute support */
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unsigned int axcache;
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};
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int ccp_pci_init(void);
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void ccp_pci_exit(void);
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int ccp_platform_init(void);
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void ccp_platform_exit(void);
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struct ccp_device *ccp_alloc_struct(struct device *dev);
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int ccp_init(struct ccp_device *ccp);
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void ccp_destroy(struct ccp_device *ccp);
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bool ccp_queues_suspended(struct ccp_device *ccp);
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irqreturn_t ccp_irq_handler(int irq, void *data);
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int ccp_run_cmd(struct ccp_cmd_queue *cmd_q, struct ccp_cmd *cmd);
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#endif
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