 a9c0688fde
			
		
	
	
	a9c0688fde
	
	
	
		
			
			This patch adds at91 smd (Soft Modem) clock implementation using common clk framework. Not used by any driver right now. Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
		
			
				
	
	
		
			171 lines
		
	
	
	
		
			4.1 KiB
			
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			171 lines
		
	
	
	
		
			4.1 KiB
			
		
	
	
	
		
			C
		
	
	
	
	
	
| /*
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|  *  Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
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|  *
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|  * This program is free software; you can redistribute it and/or modify
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|  * it under the terms of the GNU General Public License as published by
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|  * the Free Software Foundation; either version 2 of the License, or
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|  * (at your option) any later version.
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|  *
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|  */
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| 
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| #include <linux/clk-provider.h>
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| #include <linux/clkdev.h>
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| #include <linux/clk/at91_pmc.h>
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| #include <linux/of.h>
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| #include <linux/of_address.h>
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| #include <linux/io.h>
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| 
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| #include "pmc.h"
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| 
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| #define SMD_SOURCE_MAX		2
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| 
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| #define SMD_DIV_SHIFT		8
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| #define SMD_MAX_DIV		0xf
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| 
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| struct at91sam9x5_clk_smd {
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| 	struct clk_hw hw;
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| 	struct at91_pmc *pmc;
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| };
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| 
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| #define to_at91sam9x5_clk_smd(hw) \
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| 	container_of(hw, struct at91sam9x5_clk_smd, hw)
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| 
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| static unsigned long at91sam9x5_clk_smd_recalc_rate(struct clk_hw *hw,
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| 						    unsigned long parent_rate)
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| {
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| 	u32 tmp;
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| 	u8 smddiv;
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| 	struct at91sam9x5_clk_smd *smd = to_at91sam9x5_clk_smd(hw);
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| 	struct at91_pmc *pmc = smd->pmc;
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| 
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| 	tmp = pmc_read(pmc, AT91_PMC_SMD);
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| 	smddiv = (tmp & AT91_PMC_SMD_DIV) >> SMD_DIV_SHIFT;
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| 	return parent_rate / (smddiv + 1);
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| }
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| 
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| static long at91sam9x5_clk_smd_round_rate(struct clk_hw *hw, unsigned long rate,
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| 					  unsigned long *parent_rate)
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| {
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| 	unsigned long div;
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| 	unsigned long bestrate;
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| 	unsigned long tmp;
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| 
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| 	if (rate >= *parent_rate)
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| 		return *parent_rate;
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| 
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| 	div = *parent_rate / rate;
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| 	if (div > SMD_MAX_DIV)
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| 		return *parent_rate / (SMD_MAX_DIV + 1);
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| 
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| 	bestrate = *parent_rate / div;
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| 	tmp = *parent_rate / (div + 1);
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| 	if (bestrate - rate > rate - tmp)
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| 		bestrate = tmp;
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| 
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| 	return bestrate;
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| }
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| 
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| static int at91sam9x5_clk_smd_set_parent(struct clk_hw *hw, u8 index)
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| {
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| 	u32 tmp;
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| 	struct at91sam9x5_clk_smd *smd = to_at91sam9x5_clk_smd(hw);
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| 	struct at91_pmc *pmc = smd->pmc;
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| 
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| 	if (index > 1)
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| 		return -EINVAL;
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| 	tmp = pmc_read(pmc, AT91_PMC_SMD) & ~AT91_PMC_SMDS;
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| 	if (index)
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| 		tmp |= AT91_PMC_SMDS;
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| 	pmc_write(pmc, AT91_PMC_SMD, tmp);
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| 	return 0;
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| }
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| 
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| static u8 at91sam9x5_clk_smd_get_parent(struct clk_hw *hw)
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| {
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| 	struct at91sam9x5_clk_smd *smd = to_at91sam9x5_clk_smd(hw);
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| 	struct at91_pmc *pmc = smd->pmc;
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| 
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| 	return pmc_read(pmc, AT91_PMC_SMD) & AT91_PMC_SMDS;
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| }
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| 
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| static int at91sam9x5_clk_smd_set_rate(struct clk_hw *hw, unsigned long rate,
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| 				       unsigned long parent_rate)
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| {
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| 	u32 tmp;
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| 	struct at91sam9x5_clk_smd *smd = to_at91sam9x5_clk_smd(hw);
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| 	struct at91_pmc *pmc = smd->pmc;
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| 	unsigned long div = parent_rate / rate;
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| 
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| 	if (parent_rate % rate || div < 1 || div > (SMD_MAX_DIV + 1))
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| 		return -EINVAL;
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| 	tmp = pmc_read(pmc, AT91_PMC_SMD) & ~AT91_PMC_SMD_DIV;
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| 	tmp |= (div - 1) << SMD_DIV_SHIFT;
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| 	pmc_write(pmc, AT91_PMC_SMD, tmp);
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| 
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| 	return 0;
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| }
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| 
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| static const struct clk_ops at91sam9x5_smd_ops = {
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| 	.recalc_rate = at91sam9x5_clk_smd_recalc_rate,
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| 	.round_rate = at91sam9x5_clk_smd_round_rate,
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| 	.get_parent = at91sam9x5_clk_smd_get_parent,
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| 	.set_parent = at91sam9x5_clk_smd_set_parent,
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| 	.set_rate = at91sam9x5_clk_smd_set_rate,
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| };
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| 
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| static struct clk * __init
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| at91sam9x5_clk_register_smd(struct at91_pmc *pmc, const char *name,
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| 			    const char **parent_names, u8 num_parents)
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| {
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| 	struct at91sam9x5_clk_smd *smd;
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| 	struct clk *clk = NULL;
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| 	struct clk_init_data init;
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| 
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| 	smd = kzalloc(sizeof(*smd), GFP_KERNEL);
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| 	if (!smd)
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| 		return ERR_PTR(-ENOMEM);
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| 
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| 	init.name = name;
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| 	init.ops = &at91sam9x5_smd_ops;
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| 	init.parent_names = parent_names;
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| 	init.num_parents = num_parents;
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| 	init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE;
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| 
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| 	smd->hw.init = &init;
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| 	smd->pmc = pmc;
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| 
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| 	clk = clk_register(NULL, &smd->hw);
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| 	if (IS_ERR(clk))
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| 		kfree(smd);
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| 
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| 	return clk;
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| }
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| 
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| void __init of_at91sam9x5_clk_smd_setup(struct device_node *np,
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| 					struct at91_pmc *pmc)
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| {
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| 	struct clk *clk;
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| 	int i;
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| 	int num_parents;
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| 	const char *parent_names[SMD_SOURCE_MAX];
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| 	const char *name = np->name;
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| 
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| 	num_parents = of_count_phandle_with_args(np, "clocks", "#clock-cells");
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| 	if (num_parents <= 0 || num_parents > SMD_SOURCE_MAX)
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| 		return;
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| 
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| 	for (i = 0; i < num_parents; i++) {
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| 		parent_names[i] = of_clk_get_parent_name(np, i);
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| 		if (!parent_names[i])
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| 			return;
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| 	}
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| 
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| 	of_property_read_string(np, "clock-output-names", &name);
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| 
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| 	clk = at91sam9x5_clk_register_smd(pmc, name, parent_names,
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| 					  num_parents);
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| 	if (IS_ERR(clk))
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| 		return;
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| 
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| 	of_clk_add_provider(np, of_clk_src_simple_get, clk);
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| }
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