bcc5fd49a0
Newer SoCs have two different AHB interconnect. The AHB 32 bits Matrix interconnect (h32mx) has a clock that can be setup at the half of the h64mx clock (which is mck). The h32mx clock can not exceed 90 MHz. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
123 lines
2.9 KiB
C
123 lines
2.9 KiB
C
/*
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* clk-h32mx.c
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*
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* Copyright (C) 2014 Atmel
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*
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* Alexandre Belloni <alexandre.belloni@free-electrons.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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*/
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#include <linux/clk-provider.h>
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#include <linux/clkdev.h>
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#include <linux/clk/at91_pmc.h>
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#include <linux/delay.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/io.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/sched.h>
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#include <linux/wait.h>
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#include "pmc.h"
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#define H32MX_MAX_FREQ 90000000
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struct clk_sama5d4_h32mx {
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struct clk_hw hw;
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struct at91_pmc *pmc;
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};
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#define to_clk_sama5d4_h32mx(hw) container_of(hw, struct clk_sama5d4_h32mx, hw)
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static unsigned long clk_sama5d4_h32mx_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_sama5d4_h32mx *h32mxclk = to_clk_sama5d4_h32mx(hw);
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if (pmc_read(h32mxclk->pmc, AT91_PMC_MCKR) & AT91_PMC_H32MXDIV)
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return parent_rate / 2;
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if (parent_rate > H32MX_MAX_FREQ)
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pr_warn("H32MX clock is too fast\n");
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return parent_rate;
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}
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static long clk_sama5d4_h32mx_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *parent_rate)
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{
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unsigned long div;
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if (rate > *parent_rate)
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return *parent_rate;
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div = *parent_rate / 2;
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if (rate < div)
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return div;
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if (rate - div < *parent_rate - rate)
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return div;
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return *parent_rate;
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}
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static int clk_sama5d4_h32mx_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_sama5d4_h32mx *h32mxclk = to_clk_sama5d4_h32mx(hw);
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struct at91_pmc *pmc = h32mxclk->pmc;
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u32 tmp;
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if (parent_rate != rate && (parent_rate / 2) != rate)
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return -EINVAL;
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pmc_lock(pmc);
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tmp = pmc_read(pmc, AT91_PMC_MCKR) & ~AT91_PMC_H32MXDIV;
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if ((parent_rate / 2) == rate)
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tmp |= AT91_PMC_H32MXDIV;
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pmc_write(pmc, AT91_PMC_MCKR, tmp);
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pmc_unlock(pmc);
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return 0;
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}
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static const struct clk_ops h32mx_ops = {
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.recalc_rate = clk_sama5d4_h32mx_recalc_rate,
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.round_rate = clk_sama5d4_h32mx_round_rate,
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.set_rate = clk_sama5d4_h32mx_set_rate,
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};
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void __init of_sama5d4_clk_h32mx_setup(struct device_node *np,
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struct at91_pmc *pmc)
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{
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struct clk_sama5d4_h32mx *h32mxclk;
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struct clk_init_data init;
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const char *parent_name;
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struct clk *clk;
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h32mxclk = kzalloc(sizeof(*h32mxclk), GFP_KERNEL);
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if (!h32mxclk)
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return;
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parent_name = of_clk_get_parent_name(np, 0);
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init.name = np->name;
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init.ops = &h32mx_ops;
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init.parent_names = parent_name ? &parent_name : NULL;
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init.num_parents = parent_name ? 1 : 0;
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init.flags = CLK_SET_RATE_GATE;
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h32mxclk->hw.init = &init;
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h32mxclk->pmc = pmc;
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clk = clk_register(NULL, &h32mxclk->hw);
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if (!clk)
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return;
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of_clk_add_provider(np, of_clk_src_simple_get, clk);
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}
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