 8e3441ebab
			
		
	
	
	8e3441ebab
	
	
	
		
			
			The PMC module is used by perf_events, oprofile and watchdogs. Signed-off-by: Zhigang Lu <zlu@tilera.com> Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
		
			
				
	
	
		
			64 lines
		
	
	
	
		
			2.1 KiB
			
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			64 lines
		
	
	
	
		
			2.1 KiB
			
		
	
	
	
		
			C
		
	
	
	
	
	
| /*
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|  * Copyright 2014 Tilera Corporation. All Rights Reserved.
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|  *
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|  *   This program is free software; you can redistribute it and/or
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|  *   modify it under the terms of the GNU General Public License
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|  *   as published by the Free Software Foundation, version 2.
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|  *
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|  *   This program is distributed in the hope that it will be useful, but
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|  *   WITHOUT ANY WARRANTY; without even the implied warranty of
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|  *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
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|  *   NON INFRINGEMENT.  See the GNU General Public License for
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|  *   more details.
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|  */
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| 
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| #ifndef _ASM_TILE_PMC_H
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| #define _ASM_TILE_PMC_H
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| 
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| #include <linux/ptrace.h>
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| 
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| #define TILE_BASE_COUNTERS	2
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| 
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| /* Bitfields below are derived from SPR PERF_COUNT_CTL*/
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| #ifndef __tilegx__
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| /* PERF_COUNT_CTL on TILEPro */
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| #define TILE_CTL_EXCL_USER	(1 << 7) /* exclude user level */
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| #define TILE_CTL_EXCL_KERNEL	(1 << 8) /* exclude kernel level */
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| #define TILE_CTL_EXCL_HV	(1 << 9) /* exclude hypervisor level */
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| 
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| #define TILE_SEL_MASK		0x7f	/* 7 bits for event SEL,
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| 					COUNT_0_SEL */
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| #define TILE_PLM_MASK		0x780	/* 4 bits priv level msks,
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| 					COUNT_0_MASK*/
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| #define TILE_EVENT_MASK	(TILE_SEL_MASK | TILE_PLM_MASK)
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| 
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| #else /* __tilegx__*/
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| /* PERF_COUNT_CTL on TILEGx*/
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| #define TILE_CTL_EXCL_USER	(1 << 10) /* exclude user level */
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| #define TILE_CTL_EXCL_KERNEL	(1 << 11) /* exclude kernel level */
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| #define TILE_CTL_EXCL_HV	(1 << 12) /* exclude hypervisor level */
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| 
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| #define TILE_SEL_MASK		0x3f	/* 6 bits for event SEL,
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| 					COUNT_0_SEL*/
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| #define TILE_BOX_MASK		0x1c0	/* 3 bits box msks,
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| 					COUNT_0_BOX */
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| #define TILE_PLM_MASK		0x3c00	/* 4 bits priv level msks,
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| 					COUNT_0_MASK */
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| #define TILE_EVENT_MASK	(TILE_SEL_MASK | TILE_BOX_MASK | TILE_PLM_MASK)
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| #endif /* __tilegx__*/
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| 
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| /* Takes register and fault number.  Returns error to disable the interrupt. */
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| typedef int (*perf_irq_t)(struct pt_regs *, int);
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| 
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| int userspace_perf_handler(struct pt_regs *regs, int fault);
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| 
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| perf_irq_t reserve_pmc_hardware(perf_irq_t new_perf_irq);
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| void release_pmc_hardware(void);
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| 
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| unsigned long pmc_get_overflow(void);
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| void pmc_ack_overflow(unsigned long status);
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| 
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| void unmask_pmc_interrupts(void);
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| void mask_pmc_interrupts(void);
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| 
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| #endif /* _ASM_TILE_PMC_H */
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