230f984662
Now that most platforms don't need disable_fiq and arch_ret_to_user macros, we can remove the empty macros or empty entry-macro.S files. Signed-off-by: Rob Herring <rob.herring@calxeda.com> Acked-by: Jamie Iles <jamie@jamieiles.com> Acked-by: Nicolas Pitre <nico@linaro.org> Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Ryan Mallon <rmallon@gmail.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Acked-by: H Hartley Sweeten <hsweeten@visionengravers.com> Acked-by: Shawn Guo <shawn.guo@linaro.org>
37 lines
1.1 KiB
ArmAsm
37 lines
1.1 KiB
ArmAsm
/*
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* arch/arm/mach-lpc32xx/include/mach/entry-macro.S
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*
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* Author: Kevin Wells <kevin.wells@nxp.com>
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*
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* Copyright (C) 2010 NXP Semiconductors
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <mach/hardware.h>
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#include <mach/platform.h>
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#define LPC32XX_INTC_MASKED_STATUS_OFS 0x8
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.macro get_irqnr_preamble, base, tmp
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ldr \base, =IO_ADDRESS(LPC32XX_MIC_BASE)
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.endm
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/*
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* Return IRQ number in irqnr. Also return processor Z flag status in CPSR
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* as set if an interrupt is pending.
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*/
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.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
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ldr \irqstat, [\base, #LPC32XX_INTC_MASKED_STATUS_OFS]
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clz \irqnr, \irqstat
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rsb \irqnr, \irqnr, #31
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teq \irqstat, #0
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.endm
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