44b111b519
Adds support for Numascale NumaChip large-SMP systems. It is needed to enable the booting of more than ~168 cores. v2: - [Steffen] enumerate only accessible northbridges - [Daniel] rediffed and validated against 3.1-rc10 v3: - [Daniel] use x86_init core numbering override - [Daniel] cleanups as per feedback v4: - [Daniel] use updated x86_cpuinit override v5: - drop disabling interrupts locally, as ISR write is atomic; drop delay - added read-mostly annotations where appropriate - require CONFIG_SMP, so drop conditional path Workload tested on 96 cores/16 sockets. Signed-off-by: Steffen Persvold <sp@numascale.com> Signed-off-by: Daniel J Blueman <daniel@numascale-asia.com> Cc: Jesse Barnes <jbarnes@virtuousgeek.org> Link: http://lkml.kernel.org/r/1323101246-2400-1-git-send-email-daniel@numascale-asia.com Signed-off-by: Ingo Molnar <mingo@elte.hu>
167 lines
5.3 KiB
C
167 lines
5.3 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Numascale NumaConnect-Specific Header file
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*
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* Copyright (C) 2011 Numascale AS. All rights reserved.
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*
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* Send feedback to <support@numascale.com>
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*
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*/
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#ifndef _ASM_X86_NUMACHIP_NUMACHIP_CSR_H
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#define _ASM_X86_NUMACHIP_NUMACHIP_CSR_H
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#include <linux/numa.h>
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#include <linux/percpu.h>
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#include <linux/io.h>
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#include <linux/swab.h>
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#include <asm/types.h>
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#include <asm/processor.h>
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#define CSR_NODE_SHIFT 16
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#define CSR_NODE_BITS(p) (((unsigned long)(p)) << CSR_NODE_SHIFT)
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#define CSR_NODE_MASK 0x0fff /* 4K nodes */
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/* 32K CSR space, b15 indicates geo/non-geo */
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#define CSR_OFFSET_MASK 0x7fffUL
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/* Global CSR space covers all 4K possible nodes with 64K CSR space per node */
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#define NUMACHIP_GCSR_BASE 0x3fff00000000ULL
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#define NUMACHIP_GCSR_LIM 0x3fff0fffffffULL
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#define NUMACHIP_GCSR_SIZE (NUMACHIP_GCSR_LIM - NUMACHIP_GCSR_BASE + 1)
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/*
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* Local CSR space starts in global CSR space with "nodeid" = 0xfff0, however
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* when using the direct mapping on x86_64, both start and size needs to be
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* aligned with PMD_SIZE which is 2M
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*/
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#define NUMACHIP_LCSR_BASE 0x3ffffe000000ULL
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#define NUMACHIP_LCSR_LIM 0x3fffffffffffULL
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#define NUMACHIP_LCSR_SIZE (NUMACHIP_LCSR_LIM - NUMACHIP_LCSR_BASE + 1)
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static inline void *gcsr_address(int node, unsigned long offset)
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{
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return __va(NUMACHIP_GCSR_BASE | (1UL << 15) |
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CSR_NODE_BITS(node & CSR_NODE_MASK) | (offset & CSR_OFFSET_MASK));
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}
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static inline void *lcsr_address(unsigned long offset)
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{
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return __va(NUMACHIP_LCSR_BASE | (1UL << 15) |
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CSR_NODE_BITS(0xfff0) | (offset & CSR_OFFSET_MASK));
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}
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static inline unsigned int read_gcsr(int node, unsigned long offset)
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{
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return swab32(readl(gcsr_address(node, offset)));
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}
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static inline void write_gcsr(int node, unsigned long offset, unsigned int val)
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{
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writel(swab32(val), gcsr_address(node, offset));
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}
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static inline unsigned int read_lcsr(unsigned long offset)
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{
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return swab32(readl(lcsr_address(offset)));
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}
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static inline void write_lcsr(unsigned long offset, unsigned int val)
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{
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writel(swab32(val), lcsr_address(offset));
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}
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/* ========================================================================= */
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/* CSR_G0_STATE_CLEAR */
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/* ========================================================================= */
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#define CSR_G0_STATE_CLEAR (0x000 + (0 << 12))
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union numachip_csr_g0_state_clear {
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unsigned int v;
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struct numachip_csr_g0_state_clear_s {
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unsigned int _state:2;
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unsigned int _rsvd_2_6:5;
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unsigned int _lost:1;
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unsigned int _rsvd_8_31:24;
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} s;
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};
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/* ========================================================================= */
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/* CSR_G0_NODE_IDS */
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/* ========================================================================= */
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#define CSR_G0_NODE_IDS (0x008 + (0 << 12))
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union numachip_csr_g0_node_ids {
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unsigned int v;
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struct numachip_csr_g0_node_ids_s {
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unsigned int _initialid:16;
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unsigned int _nodeid:12;
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unsigned int _rsvd_28_31:4;
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} s;
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};
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/* ========================================================================= */
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/* CSR_G3_EXT_IRQ_GEN */
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/* ========================================================================= */
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#define CSR_G3_EXT_IRQ_GEN (0x030 + (3 << 12))
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union numachip_csr_g3_ext_irq_gen {
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unsigned int v;
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struct numachip_csr_g3_ext_irq_gen_s {
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unsigned int _vector:8;
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unsigned int _msgtype:3;
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unsigned int _index:5;
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unsigned int _destination_apic_id:16;
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} s;
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};
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/* ========================================================================= */
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/* CSR_G3_EXT_IRQ_STATUS */
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/* ========================================================================= */
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#define CSR_G3_EXT_IRQ_STATUS (0x034 + (3 << 12))
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union numachip_csr_g3_ext_irq_status {
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unsigned int v;
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struct numachip_csr_g3_ext_irq_status_s {
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unsigned int _result:32;
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} s;
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};
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/* ========================================================================= */
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/* CSR_G3_EXT_IRQ_DEST */
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/* ========================================================================= */
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#define CSR_G3_EXT_IRQ_DEST (0x038 + (3 << 12))
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union numachip_csr_g3_ext_irq_dest {
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unsigned int v;
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struct numachip_csr_g3_ext_irq_dest_s {
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unsigned int _irq:8;
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unsigned int _rsvd_8_31:24;
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} s;
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};
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/* ========================================================================= */
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/* CSR_G3_NC_ATT_MAP_SELECT */
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/* ========================================================================= */
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#define CSR_G3_NC_ATT_MAP_SELECT (0x7fc + (3 << 12))
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union numachip_csr_g3_nc_att_map_select {
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unsigned int v;
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struct numachip_csr_g3_nc_att_map_select_s {
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unsigned int _upper_address_bits:4;
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unsigned int _select_ram:4;
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unsigned int _rsvd_8_31:24;
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} s;
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};
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/* ========================================================================= */
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/* CSR_G3_NC_ATT_MAP_SELECT_0-255 */
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/* ========================================================================= */
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#define CSR_G3_NC_ATT_MAP_SELECT_0 (0x800 + (3 << 12))
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#endif /* _ASM_X86_NUMACHIP_NUMACHIP_CSR_H */
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