2ec941304d
Add a driver for the global clock controller found on MSM8960 based platforms. This should allow most non-multimedia device drivers to probe and control their clocks. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
118 lines
3.5 KiB
C
118 lines
3.5 KiB
C
/*
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* Copyright (c) 2013, The Linux Foundation. All rights reserved.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _DT_BINDINGS_RESET_MSM_GCC_8960_H
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#define _DT_BINDINGS_RESET_MSM_GCC_8960_H
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#define SFAB_MSS_Q6_SW_RESET 0
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#define SFAB_MSS_Q6_FW_RESET 1
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#define QDSS_STM_RESET 2
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#define AFAB_SMPSS_S_RESET 3
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#define AFAB_SMPSS_M1_RESET 4
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#define AFAB_SMPSS_M0_RESET 5
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#define AFAB_EBI1_CH0_RESET 6
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#define AFAB_EBI1_CH1_RESET 7
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#define SFAB_ADM0_M0_RESET 8
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#define SFAB_ADM0_M1_RESET 9
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#define SFAB_ADM0_M2_RESET 10
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#define ADM0_C2_RESET 11
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#define ADM0_C1_RESET 12
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#define ADM0_C0_RESET 13
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#define ADM0_PBUS_RESET 14
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#define ADM0_RESET 15
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#define QDSS_CLKS_SW_RESET 16
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#define QDSS_POR_RESET 17
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#define QDSS_TSCTR_RESET 18
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#define QDSS_HRESET_RESET 19
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#define QDSS_AXI_RESET 20
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#define QDSS_DBG_RESET 21
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#define PCIE_A_RESET 22
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#define PCIE_AUX_RESET 23
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#define PCIE_H_RESET 24
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#define SFAB_PCIE_M_RESET 25
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#define SFAB_PCIE_S_RESET 26
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#define SFAB_MSS_M_RESET 27
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#define SFAB_USB3_M_RESET 28
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#define SFAB_RIVA_M_RESET 29
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#define SFAB_LPASS_RESET 30
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#define SFAB_AFAB_M_RESET 31
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#define AFAB_SFAB_M0_RESET 32
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#define AFAB_SFAB_M1_RESET 33
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#define SFAB_SATA_S_RESET 34
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#define SFAB_DFAB_M_RESET 35
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#define DFAB_SFAB_M_RESET 36
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#define DFAB_SWAY0_RESET 37
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#define DFAB_SWAY1_RESET 38
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#define DFAB_ARB0_RESET 39
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#define DFAB_ARB1_RESET 40
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#define PPSS_PROC_RESET 41
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#define PPSS_RESET 42
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#define DMA_BAM_RESET 43
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#define SIC_TIC_RESET 44
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#define SLIMBUS_H_RESET 45
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#define SFAB_CFPB_M_RESET 46
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#define SFAB_CFPB_S_RESET 47
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#define TSIF_H_RESET 48
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#define CE1_H_RESET 49
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#define CE1_CORE_RESET 50
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#define CE1_SLEEP_RESET 51
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#define CE2_H_RESET 52
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#define CE2_CORE_RESET 53
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#define SFAB_SFPB_M_RESET 54
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#define SFAB_SFPB_S_RESET 55
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#define RPM_PROC_RESET 56
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#define PMIC_SSBI2_RESET 57
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#define SDC1_RESET 58
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#define SDC2_RESET 59
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#define SDC3_RESET 60
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#define SDC4_RESET 61
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#define SDC5_RESET 62
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#define DFAB_A2_RESET 63
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#define USB_HS1_RESET 64
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#define USB_HSIC_RESET 65
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#define USB_FS1_XCVR_RESET 66
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#define USB_FS1_RESET 67
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#define USB_FS2_XCVR_RESET 68
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#define USB_FS2_RESET 69
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#define GSBI1_RESET 70
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#define GSBI2_RESET 71
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#define GSBI3_RESET 72
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#define GSBI4_RESET 73
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#define GSBI5_RESET 74
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#define GSBI6_RESET 75
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#define GSBI7_RESET 76
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#define GSBI8_RESET 77
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#define GSBI9_RESET 78
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#define GSBI10_RESET 79
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#define GSBI11_RESET 80
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#define GSBI12_RESET 81
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#define SPDM_RESET 82
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#define TLMM_H_RESET 83
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#define SFAB_MSS_S_RESET 84
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#define MSS_SLP_RESET 85
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#define MSS_Q6SW_JTAG_RESET 86
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#define MSS_Q6FW_JTAG_RESET 87
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#define MSS_RESET 88
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#define SATA_H_RESET 89
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#define SATA_RXOOB_RESE 90
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#define SATA_PMALIVE_RESET 91
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#define SATA_SFAB_M_RESET 92
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#define TSSC_RESET 93
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#define PDM_RESET 94
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#define MPM_H_RESET 95
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#define MPM_RESET 96
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#define SFAB_SMPSS_S_RESET 97
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#define PRNG_RESET 98
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#define RIVA_RESET 99
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#endif
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