 94c73a8f97
			
		
	
	
	94c73a8f97
	
	
	
		
			
			This adds a cuboot wrapper for the AMCC PowerPC 405EZ Acadia board. The clocking code is derived from U-Boot, originally written by Stefan Roese. Signed-off-by: Josh Boyer <jwboyer@linux.ibm.com>
		
			
				
	
	
		
			174 lines
		
	
	
	
		
			4.8 KiB
			
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			174 lines
		
	
	
	
		
			4.8 KiB
			
		
	
	
	
		
			C
		
	
	
	
	
	
| /*
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|  * Old U-boot compatibility for Acadia
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|  *
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|  * Author: Josh Boyer <jwboyer@linux.vnet.ibm.com>
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|  *
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|  * Copyright 2008 IBM Corporation
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|  *
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|  * This program is free software; you can redistribute it and/or modify it
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|  * under the terms of the GNU General Public License version 2 as published
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|  * by the Free Software Foundation.
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|  */
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| 
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| #include "ops.h"
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| #include "io.h"
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| #include "dcr.h"
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| #include "stdio.h"
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| #include "4xx.h"
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| #include "44x.h"
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| #include "cuboot.h"
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| 
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| #define TARGET_4xx
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| #include "ppcboot.h"
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| 
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| static bd_t bd;
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| 
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| #define CPR_PERD0_SPIDV_MASK   0x000F0000     /* SPI Clock Divider */
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| 
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| #define PLLC_SRC_MASK	       0x20000000     /* PLL feedback source */
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| 
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| #define PLLD_FBDV_MASK	       0x1F000000     /* PLL feedback divider value */
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| #define PLLD_FWDVA_MASK        0x000F0000     /* PLL forward divider A value */
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| #define PLLD_FWDVB_MASK        0x00000700     /* PLL forward divider B value */
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| 
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| #define PRIMAD_CPUDV_MASK      0x0F000000     /* CPU Clock Divisor Mask */
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| #define PRIMAD_PLBDV_MASK      0x000F0000     /* PLB Clock Divisor Mask */
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| #define PRIMAD_OPBDV_MASK      0x00000F00     /* OPB Clock Divisor Mask */
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| #define PRIMAD_EBCDV_MASK      0x0000000F     /* EBC Clock Divisor Mask */
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| 
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| #define PERD0_PWMDV_MASK       0xFF000000     /* PWM Divider Mask */
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| #define PERD0_SPIDV_MASK       0x000F0000     /* SPI Divider Mask */
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| #define PERD0_U0DV_MASK        0x0000FF00     /* UART 0 Divider Mask */
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| #define PERD0_U1DV_MASK        0x000000FF     /* UART 1 Divider Mask */
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| 
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| static void get_clocks(void)
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| {
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| 	unsigned long sysclk, cpr_plld, cpr_pllc, cpr_primad, plloutb, i;
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| 	unsigned long pllFwdDiv, pllFwdDivB, pllFbkDiv, pllPlbDiv, pllExtBusDiv;
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| 	unsigned long pllOpbDiv, freqEBC, freqUART, freqOPB;
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| 	unsigned long div;		/* total divisor udiv * bdiv */
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| 	unsigned long umin;		/* minimum udiv	*/
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| 	unsigned short diff;		/* smallest diff */
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| 	unsigned long udiv;		/* best udiv */
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| 	unsigned short idiff;		/* current diff */
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| 	unsigned short ibdiv;		/* current bdiv */
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| 	unsigned long est;		/* current estimate */
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| 	unsigned long baud;
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| 	void *np;
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| 
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| 	/* read the sysclk value from the CPLD */
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| 	sysclk = (in_8((unsigned char *)0x80000000) == 0xc) ? 66666666 : 33333000;
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| 
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| 	/*
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| 	 * Read PLL Mode registers
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| 	 */
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| 	cpr_plld = CPR0_READ(DCRN_CPR0_PLLD);
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| 	cpr_pllc = CPR0_READ(DCRN_CPR0_PLLC);
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| 
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| 	/*
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| 	 * Determine forward divider A
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| 	 */
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| 	pllFwdDiv = ((cpr_plld & PLLD_FWDVA_MASK) >> 16);
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| 
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| 	/*
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| 	 * Determine forward divider B
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| 	 */
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| 	pllFwdDivB = ((cpr_plld & PLLD_FWDVB_MASK) >> 8);
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| 	if (pllFwdDivB == 0)
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| 		pllFwdDivB = 8;
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| 
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| 	/*
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| 	 * Determine FBK_DIV.
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| 	 */
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| 	pllFbkDiv = ((cpr_plld & PLLD_FBDV_MASK) >> 24);
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| 	if (pllFbkDiv == 0)
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| 		pllFbkDiv = 256;
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| 
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| 	/*
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| 	 * Read CPR_PRIMAD register
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| 	 */
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| 	cpr_primad = CPR0_READ(DCRN_CPR0_PRIMAD);
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| 
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| 	/*
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| 	 * Determine PLB_DIV.
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| 	 */
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| 	pllPlbDiv = ((cpr_primad & PRIMAD_PLBDV_MASK) >> 16);
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| 	if (pllPlbDiv == 0)
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| 		pllPlbDiv = 16;
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| 
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| 	/*
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| 	 * Determine EXTBUS_DIV.
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| 	 */
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| 	pllExtBusDiv = (cpr_primad & PRIMAD_EBCDV_MASK);
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| 	if (pllExtBusDiv == 0)
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| 		pllExtBusDiv = 16;
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| 
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| 	/*
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| 	 * Determine OPB_DIV.
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| 	 */
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| 	pllOpbDiv = ((cpr_primad & PRIMAD_OPBDV_MASK) >> 8);
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| 	if (pllOpbDiv == 0)
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| 		pllOpbDiv = 16;
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| 
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| 	/* There is a bug in U-Boot that prevents us from using
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| 	 * bd.bi_opbfreq because U-Boot doesn't populate it for
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| 	 * 405EZ.  We get to calculate it, yay!
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| 	 */
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| 	freqOPB = (sysclk *pllFbkDiv) /pllOpbDiv;
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| 
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| 	freqEBC = (sysclk * pllFbkDiv) / pllExtBusDiv;
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| 
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| 	plloutb = ((sysclk * ((cpr_pllc & PLLC_SRC_MASK) ?
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| 					   pllFwdDivB : pllFwdDiv) *
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| 		    pllFbkDiv) / pllFwdDivB);
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| 
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| 	np = find_node_by_alias("serial0");
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| 	if (getprop(np, "current-speed", &baud, sizeof(baud)) != sizeof(baud))
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| 		fatal("no current-speed property\n\r");
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| 
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| 	udiv = 256;			/* Assume lowest possible serial clk */
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| 	div = plloutb / (16 * baud); /* total divisor */
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| 	umin = (plloutb / freqOPB) << 1;	/* 2 x OPB divisor */
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| 	diff = 256;			/* highest possible */
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| 
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| 	/* i is the test udiv value -- start with the largest
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| 	 * possible (256) to minimize serial clock and constrain
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| 	 * search to umin.
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| 	 */
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| 	for (i = 256; i > umin; i--) {
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| 		ibdiv = div / i;
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| 		est = i * ibdiv;
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| 		idiff = (est > div) ? (est-div) : (div-est);
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| 		if (idiff == 0) {
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| 			udiv = i;
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| 			break;      /* can't do better */
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| 		} else if (idiff < diff) {
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| 			udiv = i;       /* best so far */
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| 			diff = idiff;   /* update lowest diff*/
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| 		}
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| 	}
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| 	freqUART = plloutb / udiv;
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| 
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| 	dt_fixup_cpu_clocks(bd.bi_procfreq, bd.bi_intfreq, bd.bi_plb_busfreq);
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| 	dt_fixup_clock("/plb/ebc", freqEBC);
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| 	dt_fixup_clock("/plb/opb", freqOPB);
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| 	dt_fixup_clock("/plb/opb/serial@ef600300", freqUART);
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| 	dt_fixup_clock("/plb/opb/serial@ef600400", freqUART);
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| }
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| 
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| static void acadia_fixups(void)
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| {
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| 	dt_fixup_memory(bd.bi_memstart, bd.bi_memsize);
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| 	get_clocks();
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| 	dt_fixup_mac_address_by_alias("ethernet0", bd.bi_enetaddr);
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| }
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| 	
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| void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
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| 		unsigned long r6, unsigned long r7)
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| {
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| 	CUBOOT_INIT();
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| 	platform_ops.fixups = acadia_fixups;
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| 	platform_ops.exit = ibm40x_dbcr_reset;
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| 	fdt_init(_dtb_start);
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| 	serial_console_init();
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| }
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