4a8f83409d
Add rtc clock support and clean clock support for gpio. Signed-off-by: Jett.Zhou <jtzhou@marvell.com> signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com>
100 lines
2 KiB
C
100 lines
2 KiB
C
/*
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* linux/arch/arm/mach-sa1100/clock.c
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/device.h>
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#include <linux/list.h>
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#include <linux/errno.h>
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#include <linux/err.h>
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#include <linux/string.h>
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#include <linux/clk.h>
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#include <linux/spinlock.h>
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#include <linux/mutex.h>
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#include <linux/io.h>
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#include <linux/clkdev.h>
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#include <mach/hardware.h>
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struct clkops {
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void (*enable)(struct clk *);
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void (*disable)(struct clk *);
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};
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struct clk {
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const struct clkops *ops;
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unsigned int enabled;
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};
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#define DEFINE_CLK(_name, _ops) \
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struct clk clk_##_name = { \
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.ops = _ops, \
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}
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static DEFINE_SPINLOCK(clocks_lock);
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static void clk_gpio27_enable(struct clk *clk)
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{
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/*
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* First, set up the 3.6864MHz clock on GPIO 27 for the SA-1111:
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* (SA-1110 Developer's Manual, section 9.1.2.1)
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*/
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GAFR |= GPIO_32_768kHz;
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GPDR |= GPIO_32_768kHz;
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TUCR = TUCR_3_6864MHz;
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}
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static void clk_gpio27_disable(struct clk *clk)
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{
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TUCR = 0;
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GPDR &= ~GPIO_32_768kHz;
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GAFR &= ~GPIO_32_768kHz;
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}
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int clk_enable(struct clk *clk)
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{
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unsigned long flags;
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if (clk) {
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spin_lock_irqsave(&clocks_lock, flags);
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if (clk->enabled++ == 0)
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clk->ops->enable(clk);
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spin_unlock_irqrestore(&clocks_lock, flags);
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}
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return 0;
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}
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EXPORT_SYMBOL(clk_enable);
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void clk_disable(struct clk *clk)
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{
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unsigned long flags;
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if (clk) {
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WARN_ON(clk->enabled == 0);
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spin_lock_irqsave(&clocks_lock, flags);
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if (--clk->enabled == 0)
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clk->ops->disable(clk);
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spin_unlock_irqrestore(&clocks_lock, flags);
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}
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}
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EXPORT_SYMBOL(clk_disable);
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const struct clkops clk_gpio27_ops = {
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.enable = clk_gpio27_enable,
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.disable = clk_gpio27_disable,
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};
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static DEFINE_CLK(gpio27, &clk_gpio27_ops);
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static struct clk_lookup sa11xx_clkregs[] = {
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CLKDEV_INIT("sa1111.0", NULL, &clk_gpio27),
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CLKDEV_INIT("sa1100-rtc", NULL, NULL),
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};
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static int __init sa11xx_clk_init(void)
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{
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clkdev_add_table(sa11xx_clkregs, ARRAY_SIZE(sa11xx_clkregs));
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return 0;
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}
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core_initcall(sa11xx_clk_init);
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