cc456c4e7c
The git commite7a5cd063c7b4c58417f674821d63f5eb6747e37
("x86-64, gdt: Store/load GDT for ACPI S3 or hibernate/resume path
is not needed.") assumes that for the hibernate path the booting
kernel and the resuming kernel MUST be the same. That is certainly
the case for a 32-bit kernel (see check_image_kernel and
CONFIG_ARCH_HIBERNATION_HEADER config option).
However for 64-bit kernels it is OK to have a different kernel
version (and size of the image) of the booting and resuming kernels.
Hence the above mentioned git commit introduces an regression.
This patch fixes it by introducing a 'struct desc_ptr gdt_desc'
back in the 'struct saved_context'. However instead of having in the
'save_processor_state' and 'restore_processor_state' the
store/load_gdt calls, we are only saving the GDT in the
save_processor_state.
For the restore path the lgdt operation is done in
hibernate_asm_[32|64].S in the 'restore_registers' path.
The apt reader of this description will recognize that only 64-bit
kernels need this treatment, not 32-bit. This patch adds the logic
in the 32-bit path to be more similar to 64-bit so that in the future
the unification process can take advantage of this.
[ hpa: this also reverts an inadvertent on-disk format change ]
Suggested-by: "H. Peter Anvin" <hpa@zytor.com>
Acked-by: "Rafael J. Wysocki" <rjw@sisk.pl>
Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Link: http://lkml.kernel.org/r/1367459610-9656-2-git-send-email-konrad.wilk@oracle.com
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
150 lines
3.9 KiB
ArmAsm
150 lines
3.9 KiB
ArmAsm
/*
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* Hibernation support for x86-64
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*
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* Distribute under GPLv2.
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*
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* Copyright 2007 Rafael J. Wysocki <rjw@sisk.pl>
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* Copyright 2005 Andi Kleen <ak@suse.de>
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* Copyright 2004 Pavel Machek <pavel@suse.cz>
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*
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* swsusp_arch_resume must not use any stack or any nonlocal variables while
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* copying pages:
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*
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* Its rewriting one kernel image with another. What is stack in "old"
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* image could very well be data page in "new" image, and overwriting
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* your own stack under you is bad idea.
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*/
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.text
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#include <linux/linkage.h>
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#include <asm/segment.h>
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#include <asm/page_types.h>
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#include <asm/asm-offsets.h>
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#include <asm/processor-flags.h>
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ENTRY(swsusp_arch_suspend)
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movq $saved_context, %rax
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movq %rsp, pt_regs_sp(%rax)
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movq %rbp, pt_regs_bp(%rax)
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movq %rsi, pt_regs_si(%rax)
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movq %rdi, pt_regs_di(%rax)
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movq %rbx, pt_regs_bx(%rax)
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movq %rcx, pt_regs_cx(%rax)
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movq %rdx, pt_regs_dx(%rax)
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movq %r8, pt_regs_r8(%rax)
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movq %r9, pt_regs_r9(%rax)
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movq %r10, pt_regs_r10(%rax)
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movq %r11, pt_regs_r11(%rax)
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movq %r12, pt_regs_r12(%rax)
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movq %r13, pt_regs_r13(%rax)
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movq %r14, pt_regs_r14(%rax)
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movq %r15, pt_regs_r15(%rax)
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pushfq
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popq pt_regs_flags(%rax)
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/* save the address of restore_registers */
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movq $restore_registers, %rax
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movq %rax, restore_jump_address(%rip)
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/* save cr3 */
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movq %cr3, %rax
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movq %rax, restore_cr3(%rip)
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call swsusp_save
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ret
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ENTRY(restore_image)
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/* switch to temporary page tables */
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movq $__PAGE_OFFSET, %rdx
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movq temp_level4_pgt(%rip), %rax
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subq %rdx, %rax
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movq %rax, %cr3
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/* Flush TLB */
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movq mmu_cr4_features(%rip), %rax
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movq %rax, %rdx
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andq $~(X86_CR4_PGE), %rdx
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movq %rdx, %cr4; # turn off PGE
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movq %cr3, %rcx; # flush TLB
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movq %rcx, %cr3;
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movq %rax, %cr4; # turn PGE back on
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/* prepare to jump to the image kernel */
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movq restore_jump_address(%rip), %rax
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movq restore_cr3(%rip), %rbx
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/* prepare to copy image data to their original locations */
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movq restore_pblist(%rip), %rdx
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movq relocated_restore_code(%rip), %rcx
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jmpq *%rcx
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/* code below has been relocated to a safe page */
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ENTRY(core_restore_code)
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loop:
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testq %rdx, %rdx
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jz done
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/* get addresses from the pbe and copy the page */
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movq pbe_address(%rdx), %rsi
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movq pbe_orig_address(%rdx), %rdi
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movq $(PAGE_SIZE >> 3), %rcx
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rep
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movsq
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/* progress to the next pbe */
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movq pbe_next(%rdx), %rdx
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jmp loop
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done:
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/* jump to the restore_registers address from the image header */
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jmpq *%rax
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/*
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* NOTE: This assumes that the boot kernel's text mapping covers the
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* image kernel's page containing restore_registers and the address of
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* this page is the same as in the image kernel's text mapping (it
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* should always be true, because the text mapping is linear, starting
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* from 0, and is supposed to cover the entire kernel text for every
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* kernel).
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*
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* code below belongs to the image kernel
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*/
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ENTRY(restore_registers)
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/* go back to the original page tables */
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movq %rbx, %cr3
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/* Flush TLB, including "global" things (vmalloc) */
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movq mmu_cr4_features(%rip), %rax
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movq %rax, %rdx
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andq $~(X86_CR4_PGE), %rdx
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movq %rdx, %cr4; # turn off PGE
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movq %cr3, %rcx; # flush TLB
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movq %rcx, %cr3
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movq %rax, %cr4; # turn PGE back on
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/* We don't restore %rax, it must be 0 anyway */
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movq $saved_context, %rax
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movq pt_regs_sp(%rax), %rsp
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movq pt_regs_bp(%rax), %rbp
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movq pt_regs_si(%rax), %rsi
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movq pt_regs_di(%rax), %rdi
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movq pt_regs_bx(%rax), %rbx
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movq pt_regs_cx(%rax), %rcx
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movq pt_regs_dx(%rax), %rdx
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movq pt_regs_r8(%rax), %r8
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movq pt_regs_r9(%rax), %r9
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movq pt_regs_r10(%rax), %r10
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movq pt_regs_r11(%rax), %r11
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movq pt_regs_r12(%rax), %r12
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movq pt_regs_r13(%rax), %r13
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movq pt_regs_r14(%rax), %r14
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movq pt_regs_r15(%rax), %r15
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pushq pt_regs_flags(%rax)
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popfq
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/* Saved in save_processor_state. */
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lgdt saved_context_gdt_desc(%rax)
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xorq %rax, %rax
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/* tell the hibernation core that we've just restored the memory */
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movq %rax, in_suspend(%rip)
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ret
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