9cf12167e9
This patch changes the static memory controller registers to offsets from base, prefixes them with AU1000_ to avoid silent failures due to changed addresses and introduces helpers to access them. No functional changes, comparing assembly of a few select functions shows no differences. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Cc: Linux-MIPS <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/7463/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
132 lines
5.1 KiB
C
132 lines
5.1 KiB
C
/*
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* BRIEF MODULE DESCRIPTION
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* Au1xx0 Power Management routines.
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*
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* Copyright 2001, 2008 MontaVista Software Inc.
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* Author: MontaVista Software, Inc. <source@mvista.com>
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*
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* Some of the routines are right out of init/main.c, whose
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* copyrights apply here.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/pm.h>
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#include <linux/sysctl.h>
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#include <linux/jiffies.h>
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#include <asm/uaccess.h>
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#include <asm/mach-au1x00/au1000.h>
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/*
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* We need to save/restore a bunch of core registers that are
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* either volatile or reset to some state across a processor sleep.
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* If reading a register doesn't provide a proper result for a
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* later restore, we have to provide a function for loading that
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* register and save a copy.
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*
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* We only have to save/restore registers that aren't otherwise
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* done as part of a driver pm_* function.
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*/
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static unsigned int sleep_sys_clocks[5];
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static unsigned int sleep_sys_pinfunc;
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static unsigned int sleep_static_memctlr[4][3];
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static void save_core_regs(void)
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{
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/* Clocks and PLLs. */
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sleep_sys_clocks[0] = alchemy_rdsys(AU1000_SYS_FREQCTRL0);
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sleep_sys_clocks[1] = alchemy_rdsys(AU1000_SYS_FREQCTRL1);
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sleep_sys_clocks[2] = alchemy_rdsys(AU1000_SYS_CLKSRC);
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sleep_sys_clocks[3] = alchemy_rdsys(AU1000_SYS_CPUPLL);
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sleep_sys_clocks[4] = alchemy_rdsys(AU1000_SYS_AUXPLL);
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/* pin mux config */
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sleep_sys_pinfunc = alchemy_rdsys(AU1000_SYS_PINFUNC);
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/* Save the static memory controller configuration. */
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sleep_static_memctlr[0][0] = alchemy_rdsmem(AU1000_MEM_STCFG0);
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sleep_static_memctlr[0][1] = alchemy_rdsmem(AU1000_MEM_STTIME0);
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sleep_static_memctlr[0][2] = alchemy_rdsmem(AU1000_MEM_STADDR0);
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sleep_static_memctlr[1][0] = alchemy_rdsmem(AU1000_MEM_STCFG1);
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sleep_static_memctlr[1][1] = alchemy_rdsmem(AU1000_MEM_STTIME1);
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sleep_static_memctlr[1][2] = alchemy_rdsmem(AU1000_MEM_STADDR1);
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sleep_static_memctlr[2][0] = alchemy_rdsmem(AU1000_MEM_STCFG2);
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sleep_static_memctlr[2][1] = alchemy_rdsmem(AU1000_MEM_STTIME2);
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sleep_static_memctlr[2][2] = alchemy_rdsmem(AU1000_MEM_STADDR2);
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sleep_static_memctlr[3][0] = alchemy_rdsmem(AU1000_MEM_STCFG3);
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sleep_static_memctlr[3][1] = alchemy_rdsmem(AU1000_MEM_STTIME3);
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sleep_static_memctlr[3][2] = alchemy_rdsmem(AU1000_MEM_STADDR3);
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}
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static void restore_core_regs(void)
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{
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/* restore clock configuration. Writing CPUPLL last will
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* stall a bit and stabilize other clocks (unless this is
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* one of those Au1000 with a write-only PLL, where we dont
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* have a valid value)
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*/
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alchemy_wrsys(sleep_sys_clocks[0], AU1000_SYS_FREQCTRL0);
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alchemy_wrsys(sleep_sys_clocks[1], AU1000_SYS_FREQCTRL1);
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alchemy_wrsys(sleep_sys_clocks[2], AU1000_SYS_CLKSRC);
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alchemy_wrsys(sleep_sys_clocks[4], AU1000_SYS_AUXPLL);
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if (!au1xxx_cpu_has_pll_wo())
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alchemy_wrsys(sleep_sys_clocks[3], AU1000_SYS_CPUPLL);
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alchemy_wrsys(sleep_sys_pinfunc, AU1000_SYS_PINFUNC);
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/* Restore the static memory controller configuration. */
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alchemy_wrsmem(sleep_static_memctlr[0][0], AU1000_MEM_STCFG0);
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alchemy_wrsmem(sleep_static_memctlr[0][1], AU1000_MEM_STTIME0);
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alchemy_wrsmem(sleep_static_memctlr[0][2], AU1000_MEM_STADDR0);
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alchemy_wrsmem(sleep_static_memctlr[1][0], AU1000_MEM_STCFG1);
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alchemy_wrsmem(sleep_static_memctlr[1][1], AU1000_MEM_STTIME1);
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alchemy_wrsmem(sleep_static_memctlr[1][2], AU1000_MEM_STADDR1);
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alchemy_wrsmem(sleep_static_memctlr[2][0], AU1000_MEM_STCFG2);
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alchemy_wrsmem(sleep_static_memctlr[2][1], AU1000_MEM_STTIME2);
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alchemy_wrsmem(sleep_static_memctlr[2][2], AU1000_MEM_STADDR2);
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alchemy_wrsmem(sleep_static_memctlr[3][0], AU1000_MEM_STCFG3);
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alchemy_wrsmem(sleep_static_memctlr[3][1], AU1000_MEM_STTIME3);
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alchemy_wrsmem(sleep_static_memctlr[3][2], AU1000_MEM_STADDR3);
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}
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void au_sleep(void)
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{
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save_core_regs();
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switch (alchemy_get_cputype()) {
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case ALCHEMY_CPU_AU1000:
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case ALCHEMY_CPU_AU1500:
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case ALCHEMY_CPU_AU1100:
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alchemy_sleep_au1000();
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break;
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case ALCHEMY_CPU_AU1550:
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case ALCHEMY_CPU_AU1200:
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alchemy_sleep_au1550();
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break;
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case ALCHEMY_CPU_AU1300:
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alchemy_sleep_au1300();
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break;
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}
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restore_core_regs();
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}
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