323 lines
		
	
	
	
		
			8.3 KiB
			
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			323 lines
		
	
	
	
		
			8.3 KiB
			
		
	
	
	
		
			C
		
	
	
	
	
	
| /*
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|  * Linux performance counter support for ARC700 series
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|  *
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|  * Copyright (C) 2013 Synopsys, Inc. (www.synopsys.com)
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|  *
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|  * This code is inspired by the perf support of various other architectures.
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|  *
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|  * This program is free software; you can redistribute it and/or modify
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|  * it under the terms of the GNU General Public License version 2 as
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|  * published by the Free Software Foundation.
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|  *
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|  */
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| #include <linux/errno.h>
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| #include <linux/module.h>
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| #include <linux/of.h>
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| #include <linux/perf_event.h>
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| #include <linux/platform_device.h>
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| #include <asm/arcregs.h>
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| 
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| struct arc_pmu {
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| 	struct pmu	pmu;
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| 	int		counter_size;	/* in bits */
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| 	int		n_counters;
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| 	unsigned long	used_mask[BITS_TO_LONGS(ARC_PMU_MAX_HWEVENTS)];
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| 	int		ev_hw_idx[PERF_COUNT_ARC_HW_MAX];
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| };
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| 
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| /* read counter #idx; note that counter# != event# on ARC! */
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| static uint64_t arc_pmu_read_counter(int idx)
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| {
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| 	uint32_t tmp;
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| 	uint64_t result;
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| 
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| 	/*
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| 	 * ARC supports making 'snapshots' of the counters, so we don't
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| 	 * need to care about counters wrapping to 0 underneath our feet
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| 	 */
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| 	write_aux_reg(ARC_REG_PCT_INDEX, idx);
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| 	tmp = read_aux_reg(ARC_REG_PCT_CONTROL);
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| 	write_aux_reg(ARC_REG_PCT_CONTROL, tmp | ARC_REG_PCT_CONTROL_SN);
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| 	result = (uint64_t) (read_aux_reg(ARC_REG_PCT_SNAPH)) << 32;
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| 	result |= read_aux_reg(ARC_REG_PCT_SNAPL);
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| 
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| 	return result;
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| }
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| 
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| static void arc_perf_event_update(struct perf_event *event,
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| 				  struct hw_perf_event *hwc, int idx)
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| {
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| 	struct arc_pmu *arc_pmu = container_of(event->pmu, struct arc_pmu, pmu);
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| 	uint64_t prev_raw_count, new_raw_count;
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| 	int64_t delta;
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| 
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| 	do {
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| 		prev_raw_count = local64_read(&hwc->prev_count);
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| 		new_raw_count = arc_pmu_read_counter(idx);
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| 	} while (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
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| 				 new_raw_count) != prev_raw_count);
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| 
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| 	delta = (new_raw_count - prev_raw_count) &
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| 		((1ULL << arc_pmu->counter_size) - 1ULL);
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| 
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| 	local64_add(delta, &event->count);
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| 	local64_sub(delta, &hwc->period_left);
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| }
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| 
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| static void arc_pmu_read(struct perf_event *event)
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| {
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| 	arc_perf_event_update(event, &event->hw, event->hw.idx);
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| }
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| 
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| static int arc_pmu_cache_event(u64 config)
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| {
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| 	unsigned int cache_type, cache_op, cache_result;
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| 	int ret;
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| 
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| 	cache_type	= (config >>  0) & 0xff;
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| 	cache_op	= (config >>  8) & 0xff;
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| 	cache_result	= (config >> 16) & 0xff;
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| 	if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
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| 		return -EINVAL;
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| 	if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
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| 		return -EINVAL;
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| 	if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
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| 		return -EINVAL;
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| 
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| 	ret = arc_pmu_cache_map[cache_type][cache_op][cache_result];
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| 
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| 	if (ret == CACHE_OP_UNSUPPORTED)
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| 		return -ENOENT;
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| 
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| 	return ret;
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| }
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| 
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| /* initializes hw_perf_event structure if event is supported */
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| static int arc_pmu_event_init(struct perf_event *event)
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| {
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| 	struct arc_pmu *arc_pmu = container_of(event->pmu, struct arc_pmu, pmu);
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| 	struct hw_perf_event *hwc = &event->hw;
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| 	int ret;
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| 
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| 	switch (event->attr.type) {
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| 	case PERF_TYPE_HARDWARE:
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| 		if (event->attr.config >= PERF_COUNT_HW_MAX)
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| 			return -ENOENT;
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| 		if (arc_pmu->ev_hw_idx[event->attr.config] < 0)
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| 			return -ENOENT;
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| 		hwc->config = arc_pmu->ev_hw_idx[event->attr.config];
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| 		pr_debug("initializing event %d with cfg %d\n",
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| 			 (int) event->attr.config, (int) hwc->config);
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| 		return 0;
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| 	case PERF_TYPE_HW_CACHE:
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| 		ret = arc_pmu_cache_event(event->attr.config);
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| 		if (ret < 0)
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| 			return ret;
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| 		hwc->config = arc_pmu->ev_hw_idx[ret];
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| 		return 0;
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| 	default:
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| 		return -ENOENT;
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| 	}
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| }
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| 
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| /* starts all counters */
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| static void arc_pmu_enable(struct pmu *pmu)
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| {
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| 	uint32_t tmp;
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| 	tmp = read_aux_reg(ARC_REG_PCT_CONTROL);
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| 	write_aux_reg(ARC_REG_PCT_CONTROL, (tmp & 0xffff0000) | 0x1);
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| }
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| 
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| /* stops all counters */
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| static void arc_pmu_disable(struct pmu *pmu)
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| {
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| 	uint32_t tmp;
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| 	tmp = read_aux_reg(ARC_REG_PCT_CONTROL);
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| 	write_aux_reg(ARC_REG_PCT_CONTROL, (tmp & 0xffff0000) | 0x0);
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| }
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| 
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| /*
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|  * Assigns hardware counter to hardware condition.
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|  * Note that there is no separate start/stop mechanism;
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|  * stopping is achieved by assigning the 'never' condition
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|  */
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| static void arc_pmu_start(struct perf_event *event, int flags)
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| {
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| 	struct hw_perf_event *hwc = &event->hw;
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| 	int idx = hwc->idx;
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| 
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| 	if (WARN_ON_ONCE(idx == -1))
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| 		return;
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| 
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| 	if (flags & PERF_EF_RELOAD)
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| 		WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
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| 
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| 	event->hw.state = 0;
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| 
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| 	/* enable ARC pmu here */
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| 	write_aux_reg(ARC_REG_PCT_INDEX, idx);
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| 	write_aux_reg(ARC_REG_PCT_CONFIG, hwc->config);
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| }
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| 
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| static void arc_pmu_stop(struct perf_event *event, int flags)
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| {
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| 	struct hw_perf_event *hwc = &event->hw;
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| 	int idx = hwc->idx;
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| 
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| 	if (!(event->hw.state & PERF_HES_STOPPED)) {
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| 		/* stop ARC pmu here */
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| 		write_aux_reg(ARC_REG_PCT_INDEX, idx);
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| 
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| 		/* condition code #0 is always "never" */
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| 		write_aux_reg(ARC_REG_PCT_CONFIG, 0);
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| 
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| 		event->hw.state |= PERF_HES_STOPPED;
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| 	}
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| 
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| 	if ((flags & PERF_EF_UPDATE) &&
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| 	    !(event->hw.state & PERF_HES_UPTODATE)) {
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| 		arc_perf_event_update(event, &event->hw, idx);
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| 		event->hw.state |= PERF_HES_UPTODATE;
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| 	}
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| }
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| 
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| static void arc_pmu_del(struct perf_event *event, int flags)
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| {
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| 	struct arc_pmu *arc_pmu = container_of(event->pmu, struct arc_pmu, pmu);
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| 
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| 	arc_pmu_stop(event, PERF_EF_UPDATE);
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| 	__clear_bit(event->hw.idx, arc_pmu->used_mask);
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| 
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| 	perf_event_update_userpage(event);
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| }
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| 
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| /* allocate hardware counter and optionally start counting */
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| static int arc_pmu_add(struct perf_event *event, int flags)
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| {
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| 	struct arc_pmu *arc_pmu = container_of(event->pmu, struct arc_pmu, pmu);
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| 	struct hw_perf_event *hwc = &event->hw;
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| 	int idx = hwc->idx;
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| 
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| 	if (__test_and_set_bit(idx, arc_pmu->used_mask)) {
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| 		idx = find_first_zero_bit(arc_pmu->used_mask,
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| 					  arc_pmu->n_counters);
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| 		if (idx == arc_pmu->n_counters)
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| 			return -EAGAIN;
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| 
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| 		__set_bit(idx, arc_pmu->used_mask);
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| 		hwc->idx = idx;
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| 	}
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| 
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| 	write_aux_reg(ARC_REG_PCT_INDEX, idx);
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| 	write_aux_reg(ARC_REG_PCT_CONFIG, 0);
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| 	write_aux_reg(ARC_REG_PCT_COUNTL, 0);
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| 	write_aux_reg(ARC_REG_PCT_COUNTH, 0);
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| 	local64_set(&hwc->prev_count, 0);
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| 
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| 	hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
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| 	if (flags & PERF_EF_START)
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| 		arc_pmu_start(event, PERF_EF_RELOAD);
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| 
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| 	perf_event_update_userpage(event);
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| 
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| 	return 0;
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| }
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| 
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| static int arc_pmu_device_probe(struct platform_device *pdev)
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| {
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| 	struct arc_pmu *arc_pmu;
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| 	struct arc_reg_pct_build pct_bcr;
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| 	struct arc_reg_cc_build cc_bcr;
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| 	int i, j, ret;
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| 
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| 	union cc_name {
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| 		struct {
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| 			uint32_t word0, word1;
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| 			char sentinel;
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| 		} indiv;
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| 		char str[9];
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| 	} cc_name;
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| 
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| 
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| 	READ_BCR(ARC_REG_PCT_BUILD, pct_bcr);
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| 	if (!pct_bcr.v) {
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| 		pr_err("This core does not have performance counters!\n");
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| 		return -ENODEV;
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| 	}
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| 	BUG_ON(pct_bcr.c > ARC_PMU_MAX_HWEVENTS);
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| 
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| 	READ_BCR(ARC_REG_CC_BUILD, cc_bcr);
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| 	if (!cc_bcr.v) {
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| 		pr_err("Performance counters exist, but no countable conditions?\n");
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| 		return -ENODEV;
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| 	}
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| 
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| 	arc_pmu = devm_kzalloc(&pdev->dev, sizeof(struct arc_pmu), GFP_KERNEL);
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| 	if (!arc_pmu)
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| 		return -ENOMEM;
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| 
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| 	arc_pmu->n_counters = pct_bcr.c;
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| 	arc_pmu->counter_size = 32 + (pct_bcr.s << 4);
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| 
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| 	pr_info("ARC perf\t: %d counters (%d bits), %d countable conditions\n",
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| 		arc_pmu->n_counters, arc_pmu->counter_size, cc_bcr.c);
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| 
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| 	cc_name.str[8] = 0;
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| 	for (i = 0; i < PERF_COUNT_HW_MAX; i++)
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| 		arc_pmu->ev_hw_idx[i] = -1;
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| 
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| 	for (j = 0; j < cc_bcr.c; j++) {
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| 		write_aux_reg(ARC_REG_CC_INDEX, j);
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| 		cc_name.indiv.word0 = read_aux_reg(ARC_REG_CC_NAME0);
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| 		cc_name.indiv.word1 = read_aux_reg(ARC_REG_CC_NAME1);
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| 		for (i = 0; i < ARRAY_SIZE(arc_pmu_ev_hw_map); i++) {
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| 			if (arc_pmu_ev_hw_map[i] &&
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| 			    !strcmp(arc_pmu_ev_hw_map[i], cc_name.str) &&
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| 			    strlen(arc_pmu_ev_hw_map[i])) {
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| 				pr_debug("mapping %d to idx %d with name %s\n",
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| 					 i, j, cc_name.str);
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| 				arc_pmu->ev_hw_idx[i] = j;
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| 			}
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| 		}
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| 	}
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| 
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| 	arc_pmu->pmu = (struct pmu) {
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| 		.pmu_enable	= arc_pmu_enable,
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| 		.pmu_disable	= arc_pmu_disable,
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| 		.event_init	= arc_pmu_event_init,
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| 		.add		= arc_pmu_add,
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| 		.del		= arc_pmu_del,
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| 		.start		= arc_pmu_start,
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| 		.stop		= arc_pmu_stop,
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| 		.read		= arc_pmu_read,
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| 	};
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| 
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| 	/* ARC 700 PMU does not support sampling events */
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| 	arc_pmu->pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT;
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| 
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| 	ret = perf_pmu_register(&arc_pmu->pmu, pdev->name, PERF_TYPE_RAW);
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| 
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| 	return ret;
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| }
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| 
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| #ifdef CONFIG_OF
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| static const struct of_device_id arc_pmu_match[] = {
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| 	{ .compatible = "snps,arc700-pmu" },
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| 	{},
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| };
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| MODULE_DEVICE_TABLE(of, arc_pmu_match);
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| #endif
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| 
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| static struct platform_driver arc_pmu_driver = {
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| 	.driver	= {
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| 		.name		= "arc700-pmu",
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| 		.of_match_table = of_match_ptr(arc_pmu_match),
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| 	},
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| 	.probe		= arc_pmu_device_probe,
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| };
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| 
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| module_platform_driver(arc_pmu_driver);
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| 
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| MODULE_LICENSE("GPL");
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| MODULE_AUTHOR("Mischa Jonker <mjonker@synopsys.com>");
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| MODULE_DESCRIPTION("ARC PMU driver");
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