86 lines
		
	
	
	
		
			2.2 KiB
			
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			86 lines
		
	
	
	
		
			2.2 KiB
			
		
	
	
	
		
			C
		
	
	
	
	
	
/*
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 *	include/asm-mips/i8259.h
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 *
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 *	i8259A interrupt definitions.
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 *
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 *	Copyright (C) 2003  Maciej W. Rozycki
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 *	Copyright (C) 2003  Ralf Baechle <ralf@linux-mips.org>
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 *
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 *	This program is free software; you can redistribute it and/or
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 *	modify it under the terms of the GNU General Public License
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 *	as published by the Free Software Foundation; either version
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 *	2 of the License, or (at your option) any later version.
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 */
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#ifndef _ASM_I8259_H
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#define _ASM_I8259_H
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#include <linux/compiler.h>
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#include <linux/spinlock.h>
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#include <asm/io.h>
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#include <irq.h>
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/* i8259A PIC registers */
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#define PIC_MASTER_CMD		0x20
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#define PIC_MASTER_IMR		0x21
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#define PIC_MASTER_ISR		PIC_MASTER_CMD
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#define PIC_MASTER_POLL		PIC_MASTER_ISR
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#define PIC_MASTER_OCW3		PIC_MASTER_ISR
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#define PIC_SLAVE_CMD		0xa0
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#define PIC_SLAVE_IMR		0xa1
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/* i8259A PIC related value */
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#define PIC_CASCADE_IR		2
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#define MASTER_ICW4_DEFAULT	0x01
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#define SLAVE_ICW4_DEFAULT	0x01
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#define PIC_ICW4_AEOI		2
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extern raw_spinlock_t i8259A_lock;
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extern int i8259A_irq_pending(unsigned int irq);
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extern void make_8259A_irq(unsigned int irq);
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extern void init_i8259_irqs(void);
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/*
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 * Do the traditional i8259 interrupt polling thing.  This is for the few
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 * cases where no better interrupt acknowledge method is available and we
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 * absolutely must touch the i8259.
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 */
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static inline int i8259_irq(void)
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{
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	int irq;
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	raw_spin_lock(&i8259A_lock);
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	/* Perform an interrupt acknowledge cycle on controller 1. */
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	outb(0x0C, PIC_MASTER_CMD);		/* prepare for poll */
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	irq = inb(PIC_MASTER_CMD) & 7;
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	if (irq == PIC_CASCADE_IR) {
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		/*
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		 * Interrupt is cascaded so perform interrupt
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		 * acknowledge on controller 2.
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		 */
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		outb(0x0C, PIC_SLAVE_CMD);		/* prepare for poll */
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		irq = (inb(PIC_SLAVE_CMD) & 7) + 8;
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	}
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	if (unlikely(irq == 7)) {
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		/*
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		 * This may be a spurious interrupt.
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		 *
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		 * Read the interrupt status register (ISR). If the most
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		 * significant bit is not set then there is no valid
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		 * interrupt.
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		 */
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		outb(0x0B, PIC_MASTER_ISR);		/* ISR register */
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		if(~inb(PIC_MASTER_ISR) & 0x80)
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			irq = -1;
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	}
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	raw_spin_unlock(&i8259A_lock);
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	return likely(irq >= 0) ? irq + I8259A_IRQ_BASE : irq;
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}
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#endif /* _ASM_I8259_H */
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