a683b14df8
two reasons: 1. GPIO namings and their mode definitions are conceptually not part of the PXA register definitions 2. this is actually a temporary move in the transition of PXA2xx to use MFP-alike APIs (as what PXA3xx is now doing), so that legacy code will still work and new code can be added in step by step Signed-off-by: eric miao <eric.miao@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
121 lines
2.5 KiB
C
121 lines
2.5 KiB
C
/*
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* linux/arch/arm/mach-pxa/irq.c
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*
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* Generic PXA IRQ handling
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*
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* Author: Nicolas Pitre
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* Created: Jun 15, 2001
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* Copyright: MontaVista Software Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/sysdev.h>
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#include <asm/hardware.h>
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#include <asm/irq.h>
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#include <asm/mach/irq.h>
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#include <asm/arch/pxa-regs.h>
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#include <asm/arch/pxa2xx-gpio.h>
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#include "generic.h"
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#define IRQ_BIT(n) (((n) - PXA_IRQ(0)) & 0x1f)
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#define _ICMR(n) (*((((n) - PXA_IRQ(0)) & ~0x1f) ? &ICMR2 : &ICMR))
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#define _ICLR(n) (*((((n) - PXA_IRQ(0)) & ~0x1f) ? &ICLR2 : &ICLR))
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/*
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* This is for peripheral IRQs internal to the PXA chip.
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*/
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static int pxa_internal_irq_nr;
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static void pxa_mask_irq(unsigned int irq)
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{
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_ICMR(irq) &= ~(1 << IRQ_BIT(irq));
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}
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static void pxa_unmask_irq(unsigned int irq)
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{
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_ICMR(irq) |= 1 << IRQ_BIT(irq);
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}
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static struct irq_chip pxa_internal_irq_chip = {
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.name = "SC",
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.ack = pxa_mask_irq,
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.mask = pxa_mask_irq,
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.unmask = pxa_unmask_irq,
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};
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void __init pxa_init_irq(int irq_nr, set_wake_t fn)
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{
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int irq;
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pxa_internal_irq_nr = irq_nr;
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for (irq = 0; irq < irq_nr; irq += 32) {
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_ICMR(irq) = 0; /* disable all IRQs */
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_ICLR(irq) = 0; /* all IRQs are IRQ, not FIQ */
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}
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/* only unmasked interrupts kick us out of idle */
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ICCR = 1;
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for (irq = PXA_IRQ(0); irq < PXA_IRQ(irq_nr); irq++) {
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set_irq_chip(irq, &pxa_internal_irq_chip);
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set_irq_handler(irq, handle_level_irq);
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set_irq_flags(irq, IRQF_VALID);
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}
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pxa_internal_irq_chip.set_wake = fn;
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}
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#ifdef CONFIG_PM
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static unsigned long saved_icmr[2];
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static int pxa_irq_suspend(struct sys_device *dev, pm_message_t state)
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{
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int i, irq = PXA_IRQ(0);
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for (i = 0; irq < PXA_IRQ(pxa_internal_irq_nr); i++, irq += 32) {
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saved_icmr[i] = _ICMR(irq);
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_ICMR(irq) = 0;
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}
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return 0;
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}
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static int pxa_irq_resume(struct sys_device *dev)
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{
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int i, irq = PXA_IRQ(0);
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for (i = 0; irq < PXA_IRQ(pxa_internal_irq_nr); i++, irq += 32) {
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_ICMR(irq) = saved_icmr[i];
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_ICLR(irq) = 0;
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}
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ICCR = 1;
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return 0;
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}
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#else
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#define pxa_irq_suspend NULL
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#define pxa_irq_resume NULL
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#endif
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struct sysdev_class pxa_irq_sysclass = {
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.name = "irq",
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.suspend = pxa_irq_suspend,
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.resume = pxa_irq_resume,
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};
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static int __init pxa_irq_init(void)
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{
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return sysdev_class_register(&pxa_irq_sysclass);
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}
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core_initcall(pxa_irq_init);
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