7b14f58ad6
This patch fixes the following regression that occurred during the scsi_dma_map()/unmap() changes when compiling with CONFIG_DMA_API_DEBUG=y : WARNING: at lib/dma-debug.c:496 check_unmap+0x142/0x542() Hardware name: 3w-xxxx 0000:02:02.0: DMA-API: device driver tries to free DMA memory it has not allocated [device address=0x0000000000000000] [size=36 bytes] Signed-off-by: Adam Radford <aradford@gmail.com> Signed-off-by: James Bottomley <James.Bottomley@HansenPartnership.com>
435 lines
16 KiB
C
435 lines
16 KiB
C
/*
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3w-xxxx.h -- 3ware Storage Controller device driver for Linux.
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Written By: Adam Radford <linuxraid@amcc.com>
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Modifications By: Joel Jacobson <linux@3ware.com>
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Arnaldo Carvalho de Melo <acme@conectiva.com.br>
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Brad Strand <linux@3ware.com>
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Copyright (C) 1999-2009 3ware Inc.
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Kernel compatiblity By: Andre Hedrick <andre@suse.com>
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Non-Copyright (C) 2000 Andre Hedrick <andre@suse.com>
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; version 2 of the License.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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NO WARRANTY
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THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR
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CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT
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LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
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MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is
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solely responsible for determining the appropriateness of using and
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distributing the Program and assumes all risks associated with its
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exercise of rights under this Agreement, including but not limited to
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the risks and costs of program errors, damage to or loss of data,
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programs or equipment, and unavailability or interruption of operations.
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DISCLAIMER OF LIABILITY
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NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY
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DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND
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ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
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TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
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USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED
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HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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Bugs/Comments/Suggestions should be mailed to:
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linuxraid@amcc.com
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For more information, goto:
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http://www.amcc.com
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*/
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#ifndef _3W_XXXX_H
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#define _3W_XXXX_H
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#include <linux/types.h>
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/* AEN strings */
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static char *tw_aen_string[] = {
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[0x000] = "INFO: AEN queue empty",
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[0x001] = "INFO: Soft reset occurred",
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[0x002] = "ERROR: Unit degraded: Unit #",
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[0x003] = "ERROR: Controller error",
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[0x004] = "ERROR: Rebuild failed: Unit #",
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[0x005] = "INFO: Rebuild complete: Unit #",
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[0x006] = "ERROR: Incomplete unit detected: Unit #",
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[0x007] = "INFO: Initialization complete: Unit #",
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[0x008] = "WARNING: Unclean shutdown detected: Unit #",
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[0x009] = "WARNING: ATA port timeout: Port #",
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[0x00A] = "ERROR: Drive error: Port #",
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[0x00B] = "INFO: Rebuild started: Unit #",
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[0x00C] = "INFO: Initialization started: Unit #",
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[0x00D] = "ERROR: Logical unit deleted: Unit #",
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[0x00F] = "WARNING: SMART threshold exceeded: Port #",
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[0x021] = "WARNING: ATA UDMA downgrade: Port #",
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[0x022] = "WARNING: ATA UDMA upgrade: Port #",
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[0x023] = "WARNING: Sector repair occurred: Port #",
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[0x024] = "ERROR: SBUF integrity check failure",
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[0x025] = "ERROR: Lost cached write: Port #",
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[0x026] = "ERROR: Drive ECC error detected: Port #",
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[0x027] = "ERROR: DCB checksum error: Port #",
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[0x028] = "ERROR: DCB unsupported version: Port #",
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[0x029] = "INFO: Verify started: Unit #",
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[0x02A] = "ERROR: Verify failed: Port #",
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[0x02B] = "INFO: Verify complete: Unit #",
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[0x02C] = "WARNING: Overwrote bad sector during rebuild: Port #",
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[0x02D] = "ERROR: Encountered bad sector during rebuild: Port #",
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[0x02E] = "ERROR: Replacement drive is too small: Port #",
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[0x02F] = "WARNING: Verify error: Unit not previously initialized: Unit #",
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[0x030] = "ERROR: Drive not supported: Port #"
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};
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/*
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Sense key lookup table
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Format: ESDC/flags,SenseKey,AdditionalSenseCode,AdditionalSenseCodeQualifier
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*/
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static unsigned char tw_sense_table[][4] =
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{
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/* Codes for newer firmware */
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// ATA Error SCSI Error
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{0x01, 0x03, 0x13, 0x00}, // Address mark not found Address mark not found for data field
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{0x04, 0x0b, 0x00, 0x00}, // Aborted command Aborted command
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{0x10, 0x0b, 0x14, 0x00}, // ID not found Recorded entity not found
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{0x40, 0x03, 0x11, 0x00}, // Uncorrectable ECC error Unrecovered read error
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{0x61, 0x04, 0x00, 0x00}, // Device fault Hardware error
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{0x84, 0x0b, 0x47, 0x00}, // Data CRC error SCSI parity error
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{0xd0, 0x0b, 0x00, 0x00}, // Device busy Aborted command
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{0xd1, 0x0b, 0x00, 0x00}, // Device busy Aborted command
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{0x37, 0x02, 0x04, 0x00}, // Unit offline Not ready
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{0x09, 0x02, 0x04, 0x00}, // Unrecovered disk error Not ready
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/* Codes for older firmware */
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// 3ware Error SCSI Error
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{0x51, 0x0b, 0x00, 0x00} // Unspecified Aborted command
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};
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/* Control register bit definitions */
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#define TW_CONTROL_CLEAR_HOST_INTERRUPT 0x00080000
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#define TW_CONTROL_CLEAR_ATTENTION_INTERRUPT 0x00040000
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#define TW_CONTROL_MASK_COMMAND_INTERRUPT 0x00020000
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#define TW_CONTROL_MASK_RESPONSE_INTERRUPT 0x00010000
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#define TW_CONTROL_UNMASK_COMMAND_INTERRUPT 0x00008000
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#define TW_CONTROL_UNMASK_RESPONSE_INTERRUPT 0x00004000
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#define TW_CONTROL_CLEAR_ERROR_STATUS 0x00000200
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#define TW_CONTROL_ISSUE_SOFT_RESET 0x00000100
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#define TW_CONTROL_ENABLE_INTERRUPTS 0x00000080
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#define TW_CONTROL_DISABLE_INTERRUPTS 0x00000040
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#define TW_CONTROL_ISSUE_HOST_INTERRUPT 0x00000020
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#define TW_CONTROL_CLEAR_PARITY_ERROR 0x00800000
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#define TW_CONTROL_CLEAR_QUEUE_ERROR 0x00400000
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#define TW_CONTROL_CLEAR_PCI_ABORT 0x00100000
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#define TW_CONTROL_CLEAR_SBUF_WRITE_ERROR 0x00000008
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/* Status register bit definitions */
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#define TW_STATUS_MAJOR_VERSION_MASK 0xF0000000
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#define TW_STATUS_MINOR_VERSION_MASK 0x0F000000
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#define TW_STATUS_PCI_PARITY_ERROR 0x00800000
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#define TW_STATUS_QUEUE_ERROR 0x00400000
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#define TW_STATUS_MICROCONTROLLER_ERROR 0x00200000
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#define TW_STATUS_PCI_ABORT 0x00100000
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#define TW_STATUS_HOST_INTERRUPT 0x00080000
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#define TW_STATUS_ATTENTION_INTERRUPT 0x00040000
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#define TW_STATUS_COMMAND_INTERRUPT 0x00020000
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#define TW_STATUS_RESPONSE_INTERRUPT 0x00010000
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#define TW_STATUS_COMMAND_QUEUE_FULL 0x00008000
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#define TW_STATUS_RESPONSE_QUEUE_EMPTY 0x00004000
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#define TW_STATUS_MICROCONTROLLER_READY 0x00002000
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#define TW_STATUS_COMMAND_QUEUE_EMPTY 0x00001000
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#define TW_STATUS_ALL_INTERRUPTS 0x000F0000
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#define TW_STATUS_CLEARABLE_BITS 0x00D00000
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#define TW_STATUS_EXPECTED_BITS 0x00002000
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#define TW_STATUS_UNEXPECTED_BITS 0x00F00008
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#define TW_STATUS_SBUF_WRITE_ERROR 0x00000008
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#define TW_STATUS_VALID_INTERRUPT 0x00DF0008
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/* RESPONSE QUEUE BIT DEFINITIONS */
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#define TW_RESPONSE_ID_MASK 0x00000FF0
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/* PCI related defines */
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#define TW_IO_ADDRESS_RANGE 0x10
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#define TW_DEVICE_NAME "3ware Storage Controller"
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#define TW_VENDOR_ID (0x13C1) /* 3ware */
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#define TW_DEVICE_ID (0x1000) /* Storage Controller */
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#define TW_DEVICE_ID2 (0x1001) /* 7000 series controller */
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#define TW_NUMDEVICES 2
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#define TW_PCI_CLEAR_PARITY_ERRORS 0xc100
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#define TW_PCI_CLEAR_PCI_ABORT 0x2000
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/* Command packet opcodes */
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#define TW_OP_NOP 0x0
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#define TW_OP_INIT_CONNECTION 0x1
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#define TW_OP_READ 0x2
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#define TW_OP_WRITE 0x3
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#define TW_OP_VERIFY 0x4
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#define TW_OP_GET_PARAM 0x12
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#define TW_OP_SET_PARAM 0x13
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#define TW_OP_SECTOR_INFO 0x1a
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#define TW_OP_AEN_LISTEN 0x1c
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#define TW_OP_FLUSH_CACHE 0x0e
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#define TW_CMD_PACKET 0x1d
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#define TW_CMD_PACKET_WITH_DATA 0x1f
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/* Asynchronous Event Notification (AEN) Codes */
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#define TW_AEN_QUEUE_EMPTY 0x0000
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#define TW_AEN_SOFT_RESET 0x0001
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#define TW_AEN_DEGRADED_MIRROR 0x0002
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#define TW_AEN_CONTROLLER_ERROR 0x0003
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#define TW_AEN_REBUILD_FAIL 0x0004
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#define TW_AEN_REBUILD_DONE 0x0005
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#define TW_AEN_QUEUE_FULL 0x00ff
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#define TW_AEN_TABLE_UNDEFINED 0x15
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#define TW_AEN_APORT_TIMEOUT 0x0009
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#define TW_AEN_DRIVE_ERROR 0x000A
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#define TW_AEN_SMART_FAIL 0x000F
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#define TW_AEN_SBUF_FAIL 0x0024
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/* Phase defines */
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#define TW_PHASE_INITIAL 0
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#define TW_PHASE_SINGLE 1
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#define TW_PHASE_SGLIST 2
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/* Misc defines */
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#define TW_ALIGNMENT_6000 64 /* 64 bytes */
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#define TW_ALIGNMENT_7000 4 /* 4 bytes */
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#define TW_MAX_UNITS 16
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#define TW_COMMAND_ALIGNMENT_MASK 0x1ff
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#define TW_INIT_MESSAGE_CREDITS 0x100
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#define TW_INIT_COMMAND_PACKET_SIZE 0x3
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#define TW_POLL_MAX_RETRIES 20000
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#define TW_MAX_SGL_LENGTH 62
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#define TW_ATA_PASS_SGL_MAX 60
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#define TW_Q_LENGTH 256
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#define TW_Q_START 0
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#define TW_MAX_SLOT 32
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#define TW_MAX_PCI_BUSES 255
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#define TW_MAX_RESET_TRIES 3
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#define TW_UNIT_INFORMATION_TABLE_BASE 0x300
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#define TW_MAX_CMDS_PER_LUN 254 /* 254 for io, 1 for
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chrdev ioctl, one for
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internal aen post */
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#define TW_BLOCK_SIZE 0x200 /* 512-byte blocks */
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#define TW_IOCTL 0x80
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#define TW_UNIT_ONLINE 1
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#define TW_IN_INTR 1
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#define TW_IN_RESET 2
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#define TW_IN_CHRDEV_IOCTL 3
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#define TW_MAX_SECTORS 256
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#define TW_MAX_IOCTL_SECTORS 512
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#define TW_AEN_WAIT_TIME 1000
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#define TW_IOCTL_WAIT_TIME (1 * HZ) /* 1 second */
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#define TW_ISR_DONT_COMPLETE 2
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#define TW_ISR_DONT_RESULT 3
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#define TW_IOCTL_TIMEOUT 25 /* 25 seconds */
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#define TW_IOCTL_CHRDEV_TIMEOUT 60 /* 60 seconds */
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#define TW_IOCTL_CHRDEV_FREE -1
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#define TW_DMA_MASK DMA_BIT_MASK(32)
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#define TW_MAX_CDB_LEN 16
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/* Bitmask macros to eliminate bitfields */
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/* opcode: 5, sgloffset: 3 */
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#define TW_OPSGL_IN(x,y) ((x << 5) | (y & 0x1f))
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#define TW_SGL_OUT(x) ((x >> 5) & 0x7)
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/* reserved_1: 4, response_id: 8, reserved_2: 20 */
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#define TW_RESID_OUT(x) ((x >> 4) & 0xff)
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/* unit: 4, host_id: 4 */
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#define TW_UNITHOST_IN(x,y) ((x << 4) | ( y & 0xf))
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#define TW_UNIT_OUT(x) (x & 0xf)
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/* Macros */
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#define TW_CONTROL_REG_ADDR(x) (x->base_addr)
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#define TW_STATUS_REG_ADDR(x) (x->base_addr + 0x4)
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#define TW_COMMAND_QUEUE_REG_ADDR(x) (x->base_addr + 0x8)
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#define TW_RESPONSE_QUEUE_REG_ADDR(x) (x->base_addr + 0xC)
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#define TW_CLEAR_ALL_INTERRUPTS(x) (outl(TW_STATUS_VALID_INTERRUPT, TW_CONTROL_REG_ADDR(x)))
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#define TW_CLEAR_ATTENTION_INTERRUPT(x) (outl(TW_CONTROL_CLEAR_ATTENTION_INTERRUPT, TW_CONTROL_REG_ADDR(x)))
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#define TW_CLEAR_HOST_INTERRUPT(x) (outl(TW_CONTROL_CLEAR_HOST_INTERRUPT, TW_CONTROL_REG_ADDR(x)))
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#define TW_DISABLE_INTERRUPTS(x) (outl(TW_CONTROL_DISABLE_INTERRUPTS, TW_CONTROL_REG_ADDR(x)))
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#define TW_ENABLE_AND_CLEAR_INTERRUPTS(x) (outl(TW_CONTROL_CLEAR_ATTENTION_INTERRUPT | TW_CONTROL_UNMASK_RESPONSE_INTERRUPT | TW_CONTROL_ENABLE_INTERRUPTS, TW_CONTROL_REG_ADDR(x)))
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#define TW_MASK_COMMAND_INTERRUPT(x) (outl(TW_CONTROL_MASK_COMMAND_INTERRUPT, TW_CONTROL_REG_ADDR(x)))
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#define TW_UNMASK_COMMAND_INTERRUPT(x) (outl(TW_CONTROL_UNMASK_COMMAND_INTERRUPT, TW_CONTROL_REG_ADDR(x)))
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#define TW_SOFT_RESET(x) (outl(TW_CONTROL_ISSUE_SOFT_RESET | \
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TW_CONTROL_CLEAR_HOST_INTERRUPT | \
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TW_CONTROL_CLEAR_ATTENTION_INTERRUPT | \
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TW_CONTROL_MASK_COMMAND_INTERRUPT | \
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TW_CONTROL_MASK_RESPONSE_INTERRUPT | \
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TW_CONTROL_CLEAR_ERROR_STATUS | \
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TW_CONTROL_DISABLE_INTERRUPTS, TW_CONTROL_REG_ADDR(x)))
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#define TW_STATUS_ERRORS(x) \
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(((x & TW_STATUS_PCI_ABORT) || \
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(x & TW_STATUS_PCI_PARITY_ERROR) || \
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(x & TW_STATUS_QUEUE_ERROR) || \
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(x & TW_STATUS_MICROCONTROLLER_ERROR)) && \
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(x & TW_STATUS_MICROCONTROLLER_READY))
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#ifdef TW_DEBUG
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#define dprintk(msg...) printk(msg)
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#else
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#define dprintk(msg...) do { } while(0)
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#endif
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#pragma pack(1)
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/* Scatter Gather List Entry */
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typedef struct TAG_TW_SG_Entry {
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u32 address;
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u32 length;
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} TW_SG_Entry;
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typedef unsigned char TW_Sector[512];
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/* Command Packet */
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typedef struct TW_Command {
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unsigned char opcode__sgloffset;
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unsigned char size;
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unsigned char request_id;
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unsigned char unit__hostid;
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/* Second DWORD */
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unsigned char status;
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unsigned char flags;
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union {
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unsigned short block_count;
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unsigned short parameter_count;
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unsigned short message_credits;
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} byte6;
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union {
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struct {
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u32 lba;
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TW_SG_Entry sgl[TW_MAX_SGL_LENGTH];
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u32 padding; /* pad to 512 bytes */
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} io;
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struct {
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TW_SG_Entry sgl[TW_MAX_SGL_LENGTH];
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u32 padding[2];
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} param;
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struct {
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u32 response_queue_pointer;
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u32 padding[125];
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} init_connection;
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struct {
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char version[504];
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} ioctl_miniport_version;
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} byte8;
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} TW_Command;
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#pragma pack()
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typedef struct TAG_TW_Ioctl {
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unsigned char opcode;
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unsigned short table_id;
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unsigned char parameter_id;
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unsigned char parameter_size_bytes;
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unsigned char unit_index;
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unsigned char data[1];
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} TW_Ioctl;
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#pragma pack(1)
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/* Structure for new chardev ioctls */
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typedef struct TAG_TW_New_Ioctl {
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unsigned int data_buffer_length;
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unsigned char padding [508];
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TW_Command firmware_command;
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char data_buffer[1];
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} TW_New_Ioctl;
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/* GetParam descriptor */
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typedef struct {
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unsigned short table_id;
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unsigned char parameter_id;
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unsigned char parameter_size_bytes;
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unsigned char data[1];
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} TW_Param, *PTW_Param;
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/* Response queue */
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typedef union TAG_TW_Response_Queue {
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u32 response_id;
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u32 value;
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} TW_Response_Queue;
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typedef int TW_Cmd_State;
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#define TW_S_INITIAL 0x1 /* Initial state */
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#define TW_S_STARTED 0x2 /* Id in use */
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#define TW_S_POSTED 0x4 /* Posted to the controller */
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#define TW_S_PENDING 0x8 /* Waiting to be posted in isr */
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#define TW_S_COMPLETED 0x10 /* Completed by isr */
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#define TW_S_FINISHED 0x20 /* I/O completely done */
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#define TW_START_MASK (TW_S_STARTED | TW_S_POSTED | TW_S_PENDING | TW_S_COMPLETED)
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/* Command header for ATA pass-thru */
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typedef struct TAG_TW_Passthru
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{
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unsigned char opcode__sgloffset;
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unsigned char size;
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unsigned char request_id;
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unsigned char aport__hostid;
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unsigned char status;
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unsigned char flags;
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unsigned short param;
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unsigned short features;
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unsigned short sector_count;
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unsigned short sector_num;
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unsigned short cylinder_lo;
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unsigned short cylinder_hi;
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unsigned char drive_head;
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unsigned char command;
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TW_SG_Entry sg_list[TW_ATA_PASS_SGL_MAX];
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unsigned char padding[12];
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} TW_Passthru;
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typedef struct TAG_TW_Device_Extension {
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u32 base_addr;
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unsigned long *alignment_virtual_address[TW_Q_LENGTH];
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unsigned long alignment_physical_address[TW_Q_LENGTH];
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int is_unit_present[TW_MAX_UNITS];
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unsigned long *command_packet_virtual_address[TW_Q_LENGTH];
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unsigned long command_packet_physical_address[TW_Q_LENGTH];
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struct pci_dev *tw_pci_dev;
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struct scsi_cmnd *srb[TW_Q_LENGTH];
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unsigned char free_queue[TW_Q_LENGTH];
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unsigned char free_head;
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unsigned char free_tail;
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unsigned char pending_queue[TW_Q_LENGTH];
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unsigned char pending_head;
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unsigned char pending_tail;
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TW_Cmd_State state[TW_Q_LENGTH];
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u32 posted_request_count;
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u32 max_posted_request_count;
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u32 request_count_marked_pending;
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u32 pending_request_count;
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u32 max_pending_request_count;
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u32 max_sgl_entries;
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u32 sgl_entries;
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u32 num_resets;
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u32 sector_count;
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u32 max_sector_count;
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u32 aen_count;
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struct Scsi_Host *host;
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struct mutex ioctl_lock;
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unsigned short aen_queue[TW_Q_LENGTH];
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unsigned char aen_head;
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unsigned char aen_tail;
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volatile long flags; /* long req'd for set_bit --RR */
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int reset_print;
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volatile int chrdev_request_id;
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wait_queue_head_t ioctl_wqueue;
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} TW_Device_Extension;
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#pragma pack()
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#endif /* _3W_XXXX_H */
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