527 lines
16 KiB
C
527 lines
16 KiB
C
/*
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* Copyright (C) 2007 Ben Skeggs.
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*
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sublicense, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial
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* portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
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* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
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* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
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* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "drmP.h"
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#include "drm.h"
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#include "nouveau_drv.h"
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struct nv50_instmem_priv {
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uint32_t save1700[5]; /* 0x1700->0x1710 */
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struct nouveau_gpuobj_ref *pramin_pt;
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struct nouveau_gpuobj_ref *pramin_bar;
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struct nouveau_gpuobj_ref *fb_bar;
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bool last_access_wr;
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};
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#define NV50_INSTMEM_PAGE_SHIFT 12
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#define NV50_INSTMEM_PAGE_SIZE (1 << NV50_INSTMEM_PAGE_SHIFT)
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#define NV50_INSTMEM_PT_SIZE(a) (((a) >> 12) << 3)
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/*NOTE: - Assumes 0x1700 already covers the correct MiB of PRAMIN
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*/
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#define BAR0_WI32(g, o, v) do { \
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uint32_t offset; \
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if ((g)->im_backing) { \
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offset = (g)->im_backing_start; \
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} else { \
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offset = chan->ramin->gpuobj->im_backing_start; \
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offset += (g)->im_pramin->start; \
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} \
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offset += (o); \
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nv_wr32(dev, NV_RAMIN + (offset & 0xfffff), (v)); \
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} while (0)
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int
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nv50_instmem_init(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_channel *chan;
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uint32_t c_offset, c_size, c_ramfc, c_vmpd, c_base, pt_size;
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uint32_t save_nv001700;
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uint64_t v;
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struct nv50_instmem_priv *priv;
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int ret, i;
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priv = kzalloc(sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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dev_priv->engine.instmem.priv = priv;
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/* Save state, will restore at takedown. */
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for (i = 0x1700; i <= 0x1710; i += 4)
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priv->save1700[(i-0x1700)/4] = nv_rd32(dev, i);
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/* Reserve the last MiB of VRAM, we should probably try to avoid
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* setting up the below tables over the top of the VBIOS image at
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* some point.
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*/
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dev_priv->ramin_rsvd_vram = 1 << 20;
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c_offset = dev_priv->vram_size - dev_priv->ramin_rsvd_vram;
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c_size = 128 << 10;
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c_vmpd = ((dev_priv->chipset & 0xf0) == 0x50) ? 0x1400 : 0x200;
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c_ramfc = ((dev_priv->chipset & 0xf0) == 0x50) ? 0x0 : 0x20;
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c_base = c_vmpd + 0x4000;
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pt_size = NV50_INSTMEM_PT_SIZE(dev_priv->ramin_size);
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NV_DEBUG(dev, " Rsvd VRAM base: 0x%08x\n", c_offset);
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NV_DEBUG(dev, " VBIOS image: 0x%08x\n",
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(nv_rd32(dev, 0x619f04) & ~0xff) << 8);
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NV_DEBUG(dev, " Aperture size: %d MiB\n", dev_priv->ramin_size >> 20);
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NV_DEBUG(dev, " PT size: %d KiB\n", pt_size >> 10);
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/* Determine VM layout, we need to do this first to make sure
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* we allocate enough memory for all the page tables.
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*/
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dev_priv->vm_gart_base = roundup(NV50_VM_BLOCK, NV50_VM_BLOCK);
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dev_priv->vm_gart_size = NV50_VM_BLOCK;
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dev_priv->vm_vram_base = dev_priv->vm_gart_base + dev_priv->vm_gart_size;
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dev_priv->vm_vram_size = dev_priv->vram_size;
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if (dev_priv->vm_vram_size > NV50_VM_MAX_VRAM)
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dev_priv->vm_vram_size = NV50_VM_MAX_VRAM;
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dev_priv->vm_vram_size = roundup(dev_priv->vm_vram_size, NV50_VM_BLOCK);
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dev_priv->vm_vram_pt_nr = dev_priv->vm_vram_size / NV50_VM_BLOCK;
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dev_priv->vm_end = dev_priv->vm_vram_base + dev_priv->vm_vram_size;
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NV_DEBUG(dev, "NV50VM: GART 0x%016llx-0x%016llx\n",
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dev_priv->vm_gart_base,
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dev_priv->vm_gart_base + dev_priv->vm_gart_size - 1);
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NV_DEBUG(dev, "NV50VM: VRAM 0x%016llx-0x%016llx\n",
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dev_priv->vm_vram_base,
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dev_priv->vm_vram_base + dev_priv->vm_vram_size - 1);
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c_size += dev_priv->vm_vram_pt_nr * (NV50_VM_BLOCK / 65536 * 8);
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/* Map BAR0 PRAMIN aperture over the memory we want to use */
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save_nv001700 = nv_rd32(dev, NV50_PUNK_BAR0_PRAMIN);
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nv_wr32(dev, NV50_PUNK_BAR0_PRAMIN, (c_offset >> 16));
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/* Create a fake channel, and use it as our "dummy" channels 0/127.
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* The main reason for creating a channel is so we can use the gpuobj
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* code. However, it's probably worth noting that NVIDIA also setup
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* their channels 0/127 with the same values they configure here.
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* So, there may be some other reason for doing this.
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*
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* Have to create the entire channel manually, as the real channel
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* creation code assumes we have PRAMIN access, and we don't until
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* we're done here.
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*/
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chan = kzalloc(sizeof(*chan), GFP_KERNEL);
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if (!chan)
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return -ENOMEM;
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chan->id = 0;
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chan->dev = dev;
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chan->file_priv = (struct drm_file *)-2;
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dev_priv->fifos[0] = dev_priv->fifos[127] = chan;
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/* Channel's PRAMIN object + heap */
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ret = nouveau_gpuobj_new_fake(dev, 0, c_offset, c_size, 0,
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NULL, &chan->ramin);
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if (ret)
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return ret;
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if (nouveau_mem_init_heap(&chan->ramin_heap, c_base, c_size - c_base))
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return -ENOMEM;
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/* RAMFC + zero channel's PRAMIN up to start of VM pagedir */
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ret = nouveau_gpuobj_new_fake(dev, c_ramfc, c_offset + c_ramfc,
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0x4000, 0, NULL, &chan->ramfc);
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if (ret)
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return ret;
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for (i = 0; i < c_vmpd; i += 4)
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BAR0_WI32(chan->ramin->gpuobj, i, 0);
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/* VM page directory */
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ret = nouveau_gpuobj_new_fake(dev, c_vmpd, c_offset + c_vmpd,
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0x4000, 0, &chan->vm_pd, NULL);
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if (ret)
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return ret;
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for (i = 0; i < 0x4000; i += 8) {
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BAR0_WI32(chan->vm_pd, i + 0x00, 0x00000000);
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BAR0_WI32(chan->vm_pd, i + 0x04, 0x00000000);
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}
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/* PRAMIN page table, cheat and map into VM at 0x0000000000.
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* We map the entire fake channel into the start of the PRAMIN BAR
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*/
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ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, pt_size, 0x1000,
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0, &priv->pramin_pt);
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if (ret)
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return ret;
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v = c_offset | 1;
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if (dev_priv->vram_sys_base) {
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v += dev_priv->vram_sys_base;
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v |= 0x30;
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}
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i = 0;
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while (v < dev_priv->vram_sys_base + c_offset + c_size) {
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BAR0_WI32(priv->pramin_pt->gpuobj, i + 0, lower_32_bits(v));
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BAR0_WI32(priv->pramin_pt->gpuobj, i + 4, upper_32_bits(v));
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v += 0x1000;
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i += 8;
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}
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while (i < pt_size) {
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BAR0_WI32(priv->pramin_pt->gpuobj, i + 0, 0x00000000);
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BAR0_WI32(priv->pramin_pt->gpuobj, i + 4, 0x00000000);
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i += 8;
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}
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BAR0_WI32(chan->vm_pd, 0x00, priv->pramin_pt->instance | 0x63);
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BAR0_WI32(chan->vm_pd, 0x04, 0x00000000);
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/* VRAM page table(s), mapped into VM at +1GiB */
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for (i = 0; i < dev_priv->vm_vram_pt_nr; i++) {
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ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0,
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NV50_VM_BLOCK/65536*8, 0, 0,
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&chan->vm_vram_pt[i]);
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if (ret) {
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NV_ERROR(dev, "Error creating VRAM page tables: %d\n",
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ret);
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dev_priv->vm_vram_pt_nr = i;
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return ret;
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}
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dev_priv->vm_vram_pt[i] = chan->vm_vram_pt[i]->gpuobj;
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for (v = 0; v < dev_priv->vm_vram_pt[i]->im_pramin->size;
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v += 4)
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BAR0_WI32(dev_priv->vm_vram_pt[i], v, 0);
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BAR0_WI32(chan->vm_pd, 0x10 + (i*8),
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chan->vm_vram_pt[i]->instance | 0x61);
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BAR0_WI32(chan->vm_pd, 0x14 + (i*8), 0);
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}
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/* DMA object for PRAMIN BAR */
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ret = nouveau_gpuobj_new_ref(dev, chan, chan, 0, 6*4, 16, 0,
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&priv->pramin_bar);
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if (ret)
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return ret;
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BAR0_WI32(priv->pramin_bar->gpuobj, 0x00, 0x7fc00000);
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BAR0_WI32(priv->pramin_bar->gpuobj, 0x04, dev_priv->ramin_size - 1);
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BAR0_WI32(priv->pramin_bar->gpuobj, 0x08, 0x00000000);
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BAR0_WI32(priv->pramin_bar->gpuobj, 0x0c, 0x00000000);
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BAR0_WI32(priv->pramin_bar->gpuobj, 0x10, 0x00000000);
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BAR0_WI32(priv->pramin_bar->gpuobj, 0x14, 0x00000000);
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/* DMA object for FB BAR */
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ret = nouveau_gpuobj_new_ref(dev, chan, chan, 0, 6*4, 16, 0,
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&priv->fb_bar);
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if (ret)
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return ret;
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BAR0_WI32(priv->fb_bar->gpuobj, 0x00, 0x7fc00000);
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BAR0_WI32(priv->fb_bar->gpuobj, 0x04, 0x40000000 +
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drm_get_resource_len(dev, 1) - 1);
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BAR0_WI32(priv->fb_bar->gpuobj, 0x08, 0x40000000);
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BAR0_WI32(priv->fb_bar->gpuobj, 0x0c, 0x00000000);
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BAR0_WI32(priv->fb_bar->gpuobj, 0x10, 0x00000000);
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BAR0_WI32(priv->fb_bar->gpuobj, 0x14, 0x00000000);
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/* Poke the relevant regs, and pray it works :) */
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nv_wr32(dev, NV50_PUNK_BAR_CFG_BASE, (chan->ramin->instance >> 12));
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nv_wr32(dev, NV50_PUNK_UNK1710, 0);
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nv_wr32(dev, NV50_PUNK_BAR_CFG_BASE, (chan->ramin->instance >> 12) |
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NV50_PUNK_BAR_CFG_BASE_VALID);
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nv_wr32(dev, NV50_PUNK_BAR1_CTXDMA, (priv->fb_bar->instance >> 4) |
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NV50_PUNK_BAR1_CTXDMA_VALID);
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nv_wr32(dev, NV50_PUNK_BAR3_CTXDMA, (priv->pramin_bar->instance >> 4) |
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NV50_PUNK_BAR3_CTXDMA_VALID);
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for (i = 0; i < 8; i++)
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nv_wr32(dev, 0x1900 + (i*4), 0);
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/* Assume that praying isn't enough, check that we can re-read the
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* entire fake channel back from the PRAMIN BAR */
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dev_priv->engine.instmem.prepare_access(dev, false);
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for (i = 0; i < c_size; i += 4) {
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if (nv_rd32(dev, NV_RAMIN + i) != nv_ri32(dev, i)) {
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NV_ERROR(dev, "Error reading back PRAMIN at 0x%08x\n",
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i);
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dev_priv->engine.instmem.finish_access(dev);
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return -EINVAL;
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}
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}
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dev_priv->engine.instmem.finish_access(dev);
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nv_wr32(dev, NV50_PUNK_BAR0_PRAMIN, save_nv001700);
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/* Global PRAMIN heap */
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if (nouveau_mem_init_heap(&dev_priv->ramin_heap,
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c_size, dev_priv->ramin_size - c_size)) {
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dev_priv->ramin_heap = NULL;
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NV_ERROR(dev, "Failed to init RAMIN heap\n");
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}
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/*XXX: incorrect, but needed to make hash func "work" */
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dev_priv->ramht_offset = 0x10000;
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dev_priv->ramht_bits = 9;
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dev_priv->ramht_size = (1 << dev_priv->ramht_bits);
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return 0;
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}
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void
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nv50_instmem_takedown(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nv50_instmem_priv *priv = dev_priv->engine.instmem.priv;
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struct nouveau_channel *chan = dev_priv->fifos[0];
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int i;
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NV_DEBUG(dev, "\n");
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if (!priv)
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return;
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/* Restore state from before init */
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for (i = 0x1700; i <= 0x1710; i += 4)
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nv_wr32(dev, i, priv->save1700[(i - 0x1700) / 4]);
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nouveau_gpuobj_ref_del(dev, &priv->fb_bar);
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nouveau_gpuobj_ref_del(dev, &priv->pramin_bar);
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nouveau_gpuobj_ref_del(dev, &priv->pramin_pt);
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/* Destroy dummy channel */
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if (chan) {
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for (i = 0; i < dev_priv->vm_vram_pt_nr; i++) {
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nouveau_gpuobj_ref_del(dev, &chan->vm_vram_pt[i]);
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dev_priv->vm_vram_pt[i] = NULL;
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}
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dev_priv->vm_vram_pt_nr = 0;
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nouveau_gpuobj_del(dev, &chan->vm_pd);
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nouveau_gpuobj_ref_del(dev, &chan->ramfc);
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nouveau_gpuobj_ref_del(dev, &chan->ramin);
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nouveau_mem_takedown(&chan->ramin_heap);
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dev_priv->fifos[0] = dev_priv->fifos[127] = NULL;
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kfree(chan);
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}
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dev_priv->engine.instmem.priv = NULL;
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kfree(priv);
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}
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int
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nv50_instmem_suspend(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_channel *chan = dev_priv->fifos[0];
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struct nouveau_gpuobj *ramin = chan->ramin->gpuobj;
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int i;
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ramin->im_backing_suspend = vmalloc(ramin->im_pramin->size);
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if (!ramin->im_backing_suspend)
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return -ENOMEM;
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for (i = 0; i < ramin->im_pramin->size; i += 4)
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ramin->im_backing_suspend[i/4] = nv_ri32(dev, i);
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return 0;
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}
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void
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nv50_instmem_resume(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nv50_instmem_priv *priv = dev_priv->engine.instmem.priv;
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struct nouveau_channel *chan = dev_priv->fifos[0];
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struct nouveau_gpuobj *ramin = chan->ramin->gpuobj;
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int i;
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nv_wr32(dev, NV50_PUNK_BAR0_PRAMIN, (ramin->im_backing_start >> 16));
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for (i = 0; i < ramin->im_pramin->size; i += 4)
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BAR0_WI32(ramin, i, ramin->im_backing_suspend[i/4]);
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vfree(ramin->im_backing_suspend);
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ramin->im_backing_suspend = NULL;
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/* Poke the relevant regs, and pray it works :) */
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nv_wr32(dev, NV50_PUNK_BAR_CFG_BASE, (chan->ramin->instance >> 12));
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nv_wr32(dev, NV50_PUNK_UNK1710, 0);
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nv_wr32(dev, NV50_PUNK_BAR_CFG_BASE, (chan->ramin->instance >> 12) |
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NV50_PUNK_BAR_CFG_BASE_VALID);
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nv_wr32(dev, NV50_PUNK_BAR1_CTXDMA, (priv->fb_bar->instance >> 4) |
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NV50_PUNK_BAR1_CTXDMA_VALID);
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nv_wr32(dev, NV50_PUNK_BAR3_CTXDMA, (priv->pramin_bar->instance >> 4) |
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NV50_PUNK_BAR3_CTXDMA_VALID);
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for (i = 0; i < 8; i++)
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nv_wr32(dev, 0x1900 + (i*4), 0);
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}
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int
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nv50_instmem_populate(struct drm_device *dev, struct nouveau_gpuobj *gpuobj,
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uint32_t *sz)
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{
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int ret;
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if (gpuobj->im_backing)
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return -EINVAL;
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*sz = ALIGN(*sz, NV50_INSTMEM_PAGE_SIZE);
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if (*sz == 0)
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return -EINVAL;
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ret = nouveau_bo_new(dev, NULL, *sz, 0, TTM_PL_FLAG_VRAM, 0, 0x0000,
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true, false, &gpuobj->im_backing);
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if (ret) {
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NV_ERROR(dev, "error getting PRAMIN backing pages: %d\n", ret);
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return ret;
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}
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ret = nouveau_bo_pin(gpuobj->im_backing, TTM_PL_FLAG_VRAM);
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if (ret) {
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NV_ERROR(dev, "error pinning PRAMIN backing VRAM: %d\n", ret);
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nouveau_bo_ref(NULL, &gpuobj->im_backing);
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return ret;
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}
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gpuobj->im_backing_start = gpuobj->im_backing->bo.mem.mm_node->start;
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gpuobj->im_backing_start <<= PAGE_SHIFT;
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return 0;
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}
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void
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nv50_instmem_clear(struct drm_device *dev, struct nouveau_gpuobj *gpuobj)
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{
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|
struct drm_nouveau_private *dev_priv = dev->dev_private;
|
|
|
|
if (gpuobj && gpuobj->im_backing) {
|
|
if (gpuobj->im_bound)
|
|
dev_priv->engine.instmem.unbind(dev, gpuobj);
|
|
nouveau_bo_unpin(gpuobj->im_backing);
|
|
nouveau_bo_ref(NULL, &gpuobj->im_backing);
|
|
gpuobj->im_backing = NULL;
|
|
}
|
|
}
|
|
|
|
int
|
|
nv50_instmem_bind(struct drm_device *dev, struct nouveau_gpuobj *gpuobj)
|
|
{
|
|
struct drm_nouveau_private *dev_priv = dev->dev_private;
|
|
struct nv50_instmem_priv *priv = dev_priv->engine.instmem.priv;
|
|
struct nouveau_gpuobj *pramin_pt = priv->pramin_pt->gpuobj;
|
|
uint32_t pte, pte_end;
|
|
uint64_t vram;
|
|
|
|
if (!gpuobj->im_backing || !gpuobj->im_pramin || gpuobj->im_bound)
|
|
return -EINVAL;
|
|
|
|
NV_DEBUG(dev, "st=0x%0llx sz=0x%0llx\n",
|
|
gpuobj->im_pramin->start, gpuobj->im_pramin->size);
|
|
|
|
pte = (gpuobj->im_pramin->start >> 12) << 1;
|
|
pte_end = ((gpuobj->im_pramin->size >> 12) << 1) + pte;
|
|
vram = gpuobj->im_backing_start;
|
|
|
|
NV_DEBUG(dev, "pramin=0x%llx, pte=%d, pte_end=%d\n",
|
|
gpuobj->im_pramin->start, pte, pte_end);
|
|
NV_DEBUG(dev, "first vram page: 0x%08x\n", gpuobj->im_backing_start);
|
|
|
|
vram |= 1;
|
|
if (dev_priv->vram_sys_base) {
|
|
vram += dev_priv->vram_sys_base;
|
|
vram |= 0x30;
|
|
}
|
|
|
|
dev_priv->engine.instmem.prepare_access(dev, true);
|
|
while (pte < pte_end) {
|
|
nv_wo32(dev, pramin_pt, pte++, lower_32_bits(vram));
|
|
nv_wo32(dev, pramin_pt, pte++, upper_32_bits(vram));
|
|
vram += NV50_INSTMEM_PAGE_SIZE;
|
|
}
|
|
dev_priv->engine.instmem.finish_access(dev);
|
|
|
|
nv_wr32(dev, 0x100c80, 0x00040001);
|
|
if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) {
|
|
NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (1)\n");
|
|
NV_ERROR(dev, "0x100c80 = 0x%08x\n", nv_rd32(dev, 0x100c80));
|
|
return -EBUSY;
|
|
}
|
|
|
|
nv_wr32(dev, 0x100c80, 0x00060001);
|
|
if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) {
|
|
NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n");
|
|
NV_ERROR(dev, "0x100c80 = 0x%08x\n", nv_rd32(dev, 0x100c80));
|
|
return -EBUSY;
|
|
}
|
|
|
|
gpuobj->im_bound = 1;
|
|
return 0;
|
|
}
|
|
|
|
int
|
|
nv50_instmem_unbind(struct drm_device *dev, struct nouveau_gpuobj *gpuobj)
|
|
{
|
|
struct drm_nouveau_private *dev_priv = dev->dev_private;
|
|
struct nv50_instmem_priv *priv = dev_priv->engine.instmem.priv;
|
|
uint32_t pte, pte_end;
|
|
|
|
if (gpuobj->im_bound == 0)
|
|
return -EINVAL;
|
|
|
|
pte = (gpuobj->im_pramin->start >> 12) << 1;
|
|
pte_end = ((gpuobj->im_pramin->size >> 12) << 1) + pte;
|
|
|
|
dev_priv->engine.instmem.prepare_access(dev, true);
|
|
while (pte < pte_end) {
|
|
nv_wo32(dev, priv->pramin_pt->gpuobj, pte++, 0x00000000);
|
|
nv_wo32(dev, priv->pramin_pt->gpuobj, pte++, 0x00000000);
|
|
}
|
|
dev_priv->engine.instmem.finish_access(dev);
|
|
|
|
gpuobj->im_bound = 0;
|
|
return 0;
|
|
}
|
|
|
|
void
|
|
nv50_instmem_prepare_access(struct drm_device *dev, bool write)
|
|
{
|
|
struct drm_nouveau_private *dev_priv = dev->dev_private;
|
|
struct nv50_instmem_priv *priv = dev_priv->engine.instmem.priv;
|
|
|
|
priv->last_access_wr = write;
|
|
}
|
|
|
|
void
|
|
nv50_instmem_finish_access(struct drm_device *dev)
|
|
{
|
|
struct drm_nouveau_private *dev_priv = dev->dev_private;
|
|
struct nv50_instmem_priv *priv = dev_priv->engine.instmem.priv;
|
|
|
|
if (priv->last_access_wr) {
|
|
nv_wr32(dev, 0x070000, 0x00000001);
|
|
if (!nv_wait(0x070000, 0x00000001, 0x00000000))
|
|
NV_ERROR(dev, "PRAMIN flush timeout\n");
|
|
}
|
|
}
|
|
|