b6c58b1d98
The SH7780 PCI controller supports 3 different ranges of PCI memory in addition to its PCI I/O window. In the case of 29-bit mode, only 2 memory windows are supported, while in 32-bit mode all 3 are visible. This attempts to make the resource handling completely dynamic and to permit platforms to map in as many apertures as they can handle. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
52 lines
1.9 KiB
C
52 lines
1.9 KiB
C
/*
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* Low-Level PCI Support for SH7780 targets
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*
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* Dustin McIntire (dustin@sensoria.com) (c) 2001
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* Paul Mundt (lethal@linux-sh.org) (c) 2003
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*
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* May be copied or modified under the terms of the GNU General Public
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* License. See linux/COPYING for more information.
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*
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*/
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#ifndef _PCI_SH7780_H_
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#define _PCI_SH7780_H_
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#define PCI_VENDOR_ID_RENESAS 0x1912
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#define PCI_DEVICE_ID_RENESAS_SH7781 0x0001
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#define PCI_DEVICE_ID_RENESAS_SH7780 0x0002
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#define PCI_DEVICE_ID_RENESAS_SH7763 0x0004
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#define PCI_DEVICE_ID_RENESAS_SH7785 0x0007
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/* SH7780 Control Registers */
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#define PCIECR 0xFE000008
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#define PCIECR_ENBL 0x01
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/* SH7780 Specific Values */
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#define SH7780_PCI_CONFIG_BASE 0xFD000000 /* Config space base addr */
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#define SH7780_PCI_CONFIG_SIZE 0x01000000 /* Config space size */
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#define SH7780_PCIREG_BASE 0xFE040000 /* PCI regs base address */
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/* SH7780 PCI Config Registers */
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#define SH7780_PCIIR 0x114 /* PCI Interrupt Register */
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#define SH7780_PCIIMR 0x118 /* PCI Interrupt Mask Register */
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#define SH7780_PCIAIR 0x11C /* Error Address Register */
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#define SH7780_PCICIR 0x120 /* Error Command/Data Register */
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#define SH7780_PCIAINT 0x130 /* Arbiter Interrupt Register */
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#define SH7780_PCIAINTM 0x134 /* Arbiter Int. Mask Register */
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#define SH7780_PCIBMIR 0x138 /* Error Bus Master Register */
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#define SH7780_PCIPAR 0x1C0 /* PIO Address Register */
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#define SH7780_PCIPINT 0x1CC /* Power Mgmnt Int. Register */
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#define SH7780_PCIPINTM 0x1D0 /* Power Mgmnt Mask Register */
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#define SH7780_PCIMBR(x) (0x1E0 + ((x) * 8))
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#define SH7780_PCIMBMR(x) (0x1E4 + ((x) * 8))
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#define SH7780_PCIIOBR 0x1F8
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#define SH7780_PCIIOBMR 0x1FC
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#define SH7780_PCICSCR0 0x210 /* Cache Snoop1 Cnt. Register */
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#define SH7780_PCICSCR1 0x214 /* Cache Snoop2 Cnt. Register */
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#define SH7780_PCICSAR0 0x218 /* Cache Snoop1 Addr. Register */
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#define SH7780_PCICSAR1 0x21C /* Cache Snoop2 Addr. Register */
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#endif /* _PCI_SH7780_H_ */
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