c3b28ae260
Add a sysdev to access SRAM in TXx9 SoCs via sysfs. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
488 lines
14 KiB
C
488 lines
14 KiB
C
/*
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* TX4938/4937 setup routines
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* Based on linux/arch/mips/txx9/rbtx4938/setup.c,
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* and RBTX49xx patch from CELF patch archive.
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*
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* 2003-2005 (c) MontaVista Software, Inc.
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* (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/init.h>
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#include <linux/ioport.h>
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#include <linux/delay.h>
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#include <linux/param.h>
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#include <linux/ptrace.h>
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#include <linux/mtd/physmap.h>
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#include <linux/platform_device.h>
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#include <asm/reboot.h>
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#include <asm/traps.h>
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#include <asm/txx9irq.h>
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#include <asm/txx9tmr.h>
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#include <asm/txx9pio.h>
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#include <asm/txx9/generic.h>
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#include <asm/txx9/ndfmc.h>
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#include <asm/txx9/dmac.h>
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#include <asm/txx9/tx4938.h>
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static void __init tx4938_wdr_init(void)
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{
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/* report watchdog reset status */
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if (____raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_WDRST)
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pr_warning("Watchdog reset detected at 0x%lx\n",
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read_c0_errorepc());
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/* clear WatchDogReset (W1C) */
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tx4938_ccfg_set(TX4938_CCFG_WDRST);
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/* do reset on watchdog */
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tx4938_ccfg_set(TX4938_CCFG_WR);
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}
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void __init tx4938_wdt_init(void)
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{
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txx9_wdt_init(TX4938_TMR_REG(2) & 0xfffffffffULL);
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}
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static void tx4938_machine_restart(char *command)
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{
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local_irq_disable();
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pr_emerg("Rebooting (with %s watchdog reset)...\n",
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(____raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_WDREXEN) ?
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"external" : "internal");
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/* clear watchdog status */
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tx4938_ccfg_set(TX4938_CCFG_WDRST); /* W1C */
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txx9_wdt_now(TX4938_TMR_REG(2) & 0xfffffffffULL);
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while (!(____raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_WDRST))
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;
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mdelay(10);
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if (____raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_WDREXEN) {
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pr_emerg("Rebooting (with internal watchdog reset)...\n");
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/* External WDRST failed. Do internal watchdog reset */
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tx4938_ccfg_clear(TX4938_CCFG_WDREXEN);
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}
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/* fallback */
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(*_machine_halt)();
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}
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void show_registers(struct pt_regs *regs);
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static int tx4938_be_handler(struct pt_regs *regs, int is_fixup)
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{
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int data = regs->cp0_cause & 4;
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console_verbose();
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pr_err("%cBE exception at %#lx\n", data ? 'D' : 'I', regs->cp0_epc);
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pr_err("ccfg:%llx, toea:%llx\n",
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(unsigned long long)____raw_readq(&tx4938_ccfgptr->ccfg),
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(unsigned long long)____raw_readq(&tx4938_ccfgptr->toea));
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#ifdef CONFIG_PCI
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tx4927_report_pcic_status();
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#endif
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show_registers(regs);
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panic("BusError!");
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}
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static void __init tx4938_be_init(void)
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{
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board_be_handler = tx4938_be_handler;
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}
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static struct resource tx4938_sdram_resource[4];
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static struct resource tx4938_sram_resource;
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#define TX4938_SRAM_SIZE 0x800
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void __init tx4938_setup(void)
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{
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int i;
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__u32 divmode;
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unsigned int cpuclk = 0;
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u64 ccfg;
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txx9_reg_res_init(TX4938_REV_PCODE(), TX4938_REG_BASE,
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TX4938_REG_SIZE);
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set_c0_config(TX49_CONF_CWFON);
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/* SDRAMC,EBUSC are configured by PROM */
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for (i = 0; i < 8; i++) {
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if (!(TX4938_EBUSC_CR(i) & 0x8))
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continue; /* disabled */
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txx9_ce_res[i].start = (unsigned long)TX4938_EBUSC_BA(i);
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txx9_ce_res[i].end =
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txx9_ce_res[i].start + TX4938_EBUSC_SIZE(i) - 1;
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request_resource(&iomem_resource, &txx9_ce_res[i]);
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}
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/* clocks */
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ccfg = ____raw_readq(&tx4938_ccfgptr->ccfg);
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if (txx9_master_clock) {
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/* calculate gbus_clock and cpu_clock from master_clock */
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divmode = (__u32)ccfg & TX4938_CCFG_DIVMODE_MASK;
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switch (divmode) {
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case TX4938_CCFG_DIVMODE_8:
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case TX4938_CCFG_DIVMODE_10:
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case TX4938_CCFG_DIVMODE_12:
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case TX4938_CCFG_DIVMODE_16:
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case TX4938_CCFG_DIVMODE_18:
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txx9_gbus_clock = txx9_master_clock * 4; break;
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default:
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txx9_gbus_clock = txx9_master_clock;
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}
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switch (divmode) {
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case TX4938_CCFG_DIVMODE_2:
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case TX4938_CCFG_DIVMODE_8:
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cpuclk = txx9_gbus_clock * 2; break;
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case TX4938_CCFG_DIVMODE_2_5:
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case TX4938_CCFG_DIVMODE_10:
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cpuclk = txx9_gbus_clock * 5 / 2; break;
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case TX4938_CCFG_DIVMODE_3:
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case TX4938_CCFG_DIVMODE_12:
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cpuclk = txx9_gbus_clock * 3; break;
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case TX4938_CCFG_DIVMODE_4:
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case TX4938_CCFG_DIVMODE_16:
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cpuclk = txx9_gbus_clock * 4; break;
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case TX4938_CCFG_DIVMODE_4_5:
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case TX4938_CCFG_DIVMODE_18:
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cpuclk = txx9_gbus_clock * 9 / 2; break;
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}
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txx9_cpu_clock = cpuclk;
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} else {
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if (txx9_cpu_clock == 0)
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txx9_cpu_clock = 300000000; /* 300MHz */
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/* calculate gbus_clock and master_clock from cpu_clock */
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cpuclk = txx9_cpu_clock;
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divmode = (__u32)ccfg & TX4938_CCFG_DIVMODE_MASK;
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switch (divmode) {
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case TX4938_CCFG_DIVMODE_2:
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case TX4938_CCFG_DIVMODE_8:
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txx9_gbus_clock = cpuclk / 2; break;
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case TX4938_CCFG_DIVMODE_2_5:
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case TX4938_CCFG_DIVMODE_10:
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txx9_gbus_clock = cpuclk * 2 / 5; break;
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case TX4938_CCFG_DIVMODE_3:
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case TX4938_CCFG_DIVMODE_12:
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txx9_gbus_clock = cpuclk / 3; break;
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case TX4938_CCFG_DIVMODE_4:
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case TX4938_CCFG_DIVMODE_16:
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txx9_gbus_clock = cpuclk / 4; break;
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case TX4938_CCFG_DIVMODE_4_5:
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case TX4938_CCFG_DIVMODE_18:
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txx9_gbus_clock = cpuclk * 2 / 9; break;
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}
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switch (divmode) {
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case TX4938_CCFG_DIVMODE_8:
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case TX4938_CCFG_DIVMODE_10:
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case TX4938_CCFG_DIVMODE_12:
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case TX4938_CCFG_DIVMODE_16:
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case TX4938_CCFG_DIVMODE_18:
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txx9_master_clock = txx9_gbus_clock / 4; break;
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default:
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txx9_master_clock = txx9_gbus_clock;
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}
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}
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/* change default value to udelay/mdelay take reasonable time */
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loops_per_jiffy = txx9_cpu_clock / HZ / 2;
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/* CCFG */
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tx4938_wdr_init();
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/* clear BusErrorOnWrite flag (W1C) */
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tx4938_ccfg_set(TX4938_CCFG_BEOW);
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/* enable Timeout BusError */
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if (txx9_ccfg_toeon)
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tx4938_ccfg_set(TX4938_CCFG_TOE);
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/* DMA selection */
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txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_DMASEL_ALL);
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/* Use external clock for external arbiter */
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if (!(____raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCIARB))
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txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_PCICLKEN_ALL);
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printk(KERN_INFO "%s -- %dMHz(M%dMHz) CRIR:%08x CCFG:%llx PCFG:%llx\n",
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txx9_pcode_str,
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(cpuclk + 500000) / 1000000,
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(txx9_master_clock + 500000) / 1000000,
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(__u32)____raw_readq(&tx4938_ccfgptr->crir),
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(unsigned long long)____raw_readq(&tx4938_ccfgptr->ccfg),
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(unsigned long long)____raw_readq(&tx4938_ccfgptr->pcfg));
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printk(KERN_INFO "%s SDRAMC --", txx9_pcode_str);
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for (i = 0; i < 4; i++) {
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__u64 cr = TX4938_SDRAMC_CR(i);
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unsigned long base, size;
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if (!((__u32)cr & 0x00000400))
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continue; /* disabled */
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base = (unsigned long)(cr >> 49) << 21;
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size = (((unsigned long)(cr >> 33) & 0x7fff) + 1) << 21;
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printk(" CR%d:%016llx", i, (unsigned long long)cr);
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tx4938_sdram_resource[i].name = "SDRAM";
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tx4938_sdram_resource[i].start = base;
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tx4938_sdram_resource[i].end = base + size - 1;
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tx4938_sdram_resource[i].flags = IORESOURCE_MEM;
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request_resource(&iomem_resource, &tx4938_sdram_resource[i]);
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}
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printk(" TR:%09llx\n",
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(unsigned long long)____raw_readq(&tx4938_sdramcptr->tr));
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/* SRAM */
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if (txx9_pcode == 0x4938 && ____raw_readq(&tx4938_sramcptr->cr) & 1) {
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unsigned int size = TX4938_SRAM_SIZE;
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tx4938_sram_resource.name = "SRAM";
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tx4938_sram_resource.start =
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(____raw_readq(&tx4938_sramcptr->cr) >> (39-11))
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& ~(size - 1);
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tx4938_sram_resource.end =
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tx4938_sram_resource.start + TX4938_SRAM_SIZE - 1;
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tx4938_sram_resource.flags = IORESOURCE_MEM;
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request_resource(&iomem_resource, &tx4938_sram_resource);
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}
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/* TMR */
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/* disable all timers */
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for (i = 0; i < TX4938_NR_TMR; i++)
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txx9_tmr_init(TX4938_TMR_REG(i) & 0xfffffffffULL);
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/* PIO */
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txx9_gpio_init(TX4938_PIO_REG & 0xfffffffffULL, 0, TX4938_NUM_PIO);
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__raw_writel(0, &tx4938_pioptr->maskcpu);
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__raw_writel(0, &tx4938_pioptr->maskext);
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if (txx9_pcode == 0x4938) {
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__u64 pcfg = ____raw_readq(&tx4938_ccfgptr->pcfg);
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/* set PCIC1 reset */
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txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIC1RST);
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if (pcfg & (TX4938_PCFG_ETH0_SEL | TX4938_PCFG_ETH1_SEL)) {
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mdelay(1); /* at least 128 cpu clock */
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/* clear PCIC1 reset */
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txx9_clear64(&tx4938_ccfgptr->clkctr,
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TX4938_CLKCTR_PCIC1RST);
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} else {
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printk(KERN_INFO "%s: stop PCIC1\n", txx9_pcode_str);
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/* stop PCIC1 */
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txx9_set64(&tx4938_ccfgptr->clkctr,
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TX4938_CLKCTR_PCIC1CKD);
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}
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if (!(pcfg & TX4938_PCFG_ETH0_SEL)) {
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printk(KERN_INFO "%s: stop ETH0\n", txx9_pcode_str);
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txx9_set64(&tx4938_ccfgptr->clkctr,
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TX4938_CLKCTR_ETH0RST);
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txx9_set64(&tx4938_ccfgptr->clkctr,
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TX4938_CLKCTR_ETH0CKD);
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}
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if (!(pcfg & TX4938_PCFG_ETH1_SEL)) {
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printk(KERN_INFO "%s: stop ETH1\n", txx9_pcode_str);
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txx9_set64(&tx4938_ccfgptr->clkctr,
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TX4938_CLKCTR_ETH1RST);
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txx9_set64(&tx4938_ccfgptr->clkctr,
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TX4938_CLKCTR_ETH1CKD);
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}
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}
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_machine_restart = tx4938_machine_restart;
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board_be_init = tx4938_be_init;
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}
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void __init tx4938_time_init(unsigned int tmrnr)
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{
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if (____raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_TINTDIS)
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txx9_clockevent_init(TX4938_TMR_REG(tmrnr) & 0xfffffffffULL,
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TXX9_IRQ_BASE + TX4938_IR_TMR(tmrnr),
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TXX9_IMCLK);
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}
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void __init tx4938_sio_init(unsigned int sclk, unsigned int cts_mask)
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{
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int i;
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unsigned int ch_mask = 0;
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if (__raw_readq(&tx4938_ccfgptr->pcfg) & TX4938_PCFG_ETH0_SEL)
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ch_mask |= 1 << 1; /* disable SIO1 by PCFG setting */
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for (i = 0; i < 2; i++) {
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if ((1 << i) & ch_mask)
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continue;
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txx9_sio_init(TX4938_SIO_REG(i) & 0xfffffffffULL,
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TXX9_IRQ_BASE + TX4938_IR_SIO(i),
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i, sclk, (1 << i) & cts_mask);
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}
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}
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void __init tx4938_spi_init(int busid)
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{
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txx9_spi_init(busid, TX4938_SPI_REG & 0xfffffffffULL,
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TXX9_IRQ_BASE + TX4938_IR_SPI);
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}
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void __init tx4938_ethaddr_init(unsigned char *addr0, unsigned char *addr1)
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{
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u64 pcfg = __raw_readq(&tx4938_ccfgptr->pcfg);
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if (addr0 && (pcfg & TX4938_PCFG_ETH0_SEL))
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txx9_ethaddr_init(TXX9_IRQ_BASE + TX4938_IR_ETH0, addr0);
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if (addr1 && (pcfg & TX4938_PCFG_ETH1_SEL))
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txx9_ethaddr_init(TXX9_IRQ_BASE + TX4938_IR_ETH1, addr1);
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}
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void __init tx4938_mtd_init(int ch)
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{
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struct physmap_flash_data pdata = {
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.width = TX4938_EBUSC_WIDTH(ch) / 8,
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};
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unsigned long start = txx9_ce_res[ch].start;
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unsigned long size = txx9_ce_res[ch].end - start + 1;
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if (!(TX4938_EBUSC_CR(ch) & 0x8))
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return; /* disabled */
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txx9_physmap_flash_init(ch, start, size, &pdata);
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}
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void __init tx4938_ata_init(unsigned int irq, unsigned int shift, int tune)
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{
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struct platform_device *pdev;
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struct resource res[] = {
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{
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/* .start and .end are filled in later */
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.flags = IORESOURCE_MEM,
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}, {
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.start = irq,
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.flags = IORESOURCE_IRQ,
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},
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};
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struct tx4938ide_platform_info pdata = {
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.ioport_shift = shift,
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/*
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* The IDE driver should not change bus timings if other ISA
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* devices existed.
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*/
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.gbus_clock = tune ? txx9_gbus_clock : 0,
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};
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u64 ebccr;
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int i;
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if ((__raw_readq(&tx4938_ccfgptr->pcfg) &
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(TX4938_PCFG_ATA_SEL | TX4938_PCFG_NDF_SEL))
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!= TX4938_PCFG_ATA_SEL)
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return;
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for (i = 0; i < 8; i++) {
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/* check EBCCRn.ISA, EBCCRn.BSZ, EBCCRn.ME */
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ebccr = __raw_readq(&tx4938_ebuscptr->cr[i]);
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if ((ebccr & 0x00f00008) == 0x00e00008)
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break;
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}
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if (i == 8)
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return;
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pdata.ebus_ch = i;
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res[0].start = ((ebccr >> 48) << 20) + 0x10000;
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res[0].end = res[0].start + 0x20000 - 1;
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pdev = platform_device_alloc("tx4938ide", -1);
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if (!pdev ||
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platform_device_add_resources(pdev, res, ARRAY_SIZE(res)) ||
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platform_device_add_data(pdev, &pdata, sizeof(pdata)) ||
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platform_device_add(pdev))
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platform_device_put(pdev);
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}
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void __init tx4938_ndfmc_init(unsigned int hold, unsigned int spw)
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{
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struct txx9ndfmc_platform_data plat_data = {
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.shift = 1,
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.gbus_clock = txx9_gbus_clock,
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.hold = hold,
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.spw = spw,
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.ch_mask = 1,
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};
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unsigned long baseaddr = TX4938_NDFMC_REG & 0xfffffffffULL;
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#ifdef __BIG_ENDIAN
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baseaddr += 4;
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#endif
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if ((__raw_readq(&tx4938_ccfgptr->pcfg) &
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(TX4938_PCFG_ATA_SEL|TX4938_PCFG_ISA_SEL|TX4938_PCFG_NDF_SEL)) ==
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TX4938_PCFG_NDF_SEL)
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txx9_ndfmc_init(baseaddr, &plat_data);
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}
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void __init tx4938_dmac_init(int memcpy_chan0, int memcpy_chan1)
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{
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struct txx9dmac_platform_data plat_data = {
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.have_64bit_regs = true,
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};
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int i;
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for (i = 0; i < 2; i++) {
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plat_data.memcpy_chan = i ? memcpy_chan1 : memcpy_chan0;
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txx9_dmac_init(i, TX4938_DMA_REG(i) & 0xfffffffffULL,
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TXX9_IRQ_BASE + TX4938_IR_DMA(i, 0),
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|
&plat_data);
|
|
}
|
|
}
|
|
|
|
void __init tx4938_aclc_init(void)
|
|
{
|
|
u64 pcfg = __raw_readq(&tx4938_ccfgptr->pcfg);
|
|
|
|
if ((pcfg & TX4938_PCFG_SEL2) &&
|
|
!(pcfg & TX4938_PCFG_ETH0_SEL))
|
|
txx9_aclc_init(TX4938_ACLC_REG & 0xfffffffffULL,
|
|
TXX9_IRQ_BASE + TX4938_IR_ACLC,
|
|
1, 0, 1);
|
|
}
|
|
|
|
void __init tx4938_sramc_init(void)
|
|
{
|
|
if (tx4938_sram_resource.start)
|
|
txx9_sramc_init(&tx4938_sram_resource);
|
|
}
|
|
|
|
static void __init tx4938_stop_unused_modules(void)
|
|
{
|
|
__u64 pcfg, rst = 0, ckd = 0;
|
|
char buf[128];
|
|
|
|
buf[0] = '\0';
|
|
local_irq_disable();
|
|
pcfg = ____raw_readq(&tx4938_ccfgptr->pcfg);
|
|
switch (txx9_pcode) {
|
|
case 0x4937:
|
|
if (!(pcfg & TX4938_PCFG_SEL2)) {
|
|
rst |= TX4938_CLKCTR_ACLRST;
|
|
ckd |= TX4938_CLKCTR_ACLCKD;
|
|
strcat(buf, " ACLC");
|
|
}
|
|
break;
|
|
case 0x4938:
|
|
if (!(pcfg & TX4938_PCFG_SEL2) ||
|
|
(pcfg & TX4938_PCFG_ETH0_SEL)) {
|
|
rst |= TX4938_CLKCTR_ACLRST;
|
|
ckd |= TX4938_CLKCTR_ACLCKD;
|
|
strcat(buf, " ACLC");
|
|
}
|
|
if ((pcfg &
|
|
(TX4938_PCFG_ATA_SEL | TX4938_PCFG_ISA_SEL |
|
|
TX4938_PCFG_NDF_SEL))
|
|
!= TX4938_PCFG_NDF_SEL) {
|
|
rst |= TX4938_CLKCTR_NDFRST;
|
|
ckd |= TX4938_CLKCTR_NDFCKD;
|
|
strcat(buf, " NDFMC");
|
|
}
|
|
if (!(pcfg & TX4938_PCFG_SPI_SEL)) {
|
|
rst |= TX4938_CLKCTR_SPIRST;
|
|
ckd |= TX4938_CLKCTR_SPICKD;
|
|
strcat(buf, " SPI");
|
|
}
|
|
break;
|
|
}
|
|
if (rst | ckd) {
|
|
txx9_set64(&tx4938_ccfgptr->clkctr, rst);
|
|
txx9_set64(&tx4938_ccfgptr->clkctr, ckd);
|
|
}
|
|
local_irq_enable();
|
|
if (buf[0])
|
|
pr_info("%s: stop%s\n", txx9_pcode_str, buf);
|
|
}
|
|
|
|
static int __init tx4938_late_init(void)
|
|
{
|
|
if (txx9_pcode != 0x4937 && txx9_pcode != 0x4938)
|
|
return -ENODEV;
|
|
tx4938_stop_unused_modules();
|
|
return 0;
|
|
}
|
|
late_initcall(tx4938_late_init);
|